#
# Patch managed by http://www.holgerschurig.de/patcher.html
#

--- linux-2.6.10-rc1/drivers/video/Kconfig~w100
+++ linux-2.6.10-rc1/drivers/video/Kconfig
@@ -987,6 +987,19 @@
 	  say M here and read <file:Documentation/modules.txt>.
 
 	  If unsure, say N.
+	  
+config FB_W100
+	tristate "W100 frame buffer support"
+	depends on FB && (MACH_CORGI || MACH_SHEPHERD || MACH_HUSKY)
+	---help---
+	  Frame buffer driver for the w100 as found on the Sharp SL-Cxx series. 
+
+	  This driver is also available as a module ( = code which can be
+	  inserted and removed from the running kernel whenever you want). The
+	  module will be called vfb. If you want to compile it as a module,
+	  say M here and read <file:Documentation/modules.txt>.
+
+	  If unsure, say N.
 
 config FB_PXA_PARAMETERS
 	bool "PXA LCD command line parameters"
--- linux-2.6.10-rc1/drivers/video/Makefile~w100
+++ linux-2.6.10-rc1/drivers/video/Makefile
@@ -89,6 +89,7 @@
 obj-$(CONFIG_FB_CIRRUS)		  += cirrusfb.o cfbfillrect.o cfbimgblt.o cfbcopyarea.o
 obj-$(CONFIG_FB_ASILIANT)	  += asiliantfb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o
 obj-$(CONFIG_FB_PXA)		  += pxafb.o cfbimgblt.o cfbcopyarea.o cfbfillrect.o
+obj-$(CONFIG_FB_W100)		   += w100fb.o cfbimgblt.o cfbcopyarea.o corgi_backlight.o cfbfillrect.o 
 
 # Platform or fallback drivers go here
 obj-$(CONFIG_FB_VESA)             += vesafb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o
--- /dev/null
+++ linux-2.6.10-rc1/drivers/video/corgi_backlight.c
@@ -0,0 +1,396 @@
+/*
+ * linux/drivers/video/corgi_frontlight.c 
+ *
+ * (C) Copyright 2002 SHARP
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on:
+ *
+ * linux/drivers/video/poodle_frontlight.c 
+ *
+ * (C) Copyright 2001 Lineo Japan, Inc.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on:
+ *
+ * linux/drivers/video/collie_frontlight.c 
+ *
+ * (C) Copyright 2001 Lineo Japan, Inc.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on:
+ *   drivers/video/sa1100_frontlight.c
+ *   Initial Version by: Nicholas Mistry (nmistry@lhsl.com)
+ *
+ * ChangeLog:
+ *   02-Dec-2002 SHARP   for SL-C700
+ *   01-Apr-2003 Sharp   for SL-C750
+ */
+ 
+#define DEBUG 1
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+
+#include <linux/pm.h>
+
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+//#include <asm/proc/pgtable.h>
+
+#include <video/corgi_backlight.h>
+#include <asm/arch-pxa/corgi.h>
+
+#include <linux/interrupt.h>
+
+
+static int is_corgibl_pm = 0;
+
+#define CORGI_LIGHT_SETTING 7     // range setting : 0(OFF) dim 1 2 3 4 5(MAX)
+#define CORGI_LIGHT_DEFAULT 6
+static int is_corgibl_blank = 0;
+int counter_step_contrast = CORGI_LIGHT_DEFAULT;
+static corgibl_limit = CORGI_LIGHT_SETTING - 1;
+
+static int counter_step_save     = 0;
+
+static int corgibl_ioctl(struct inode* inode,
+						 struct file*  filp,
+						 unsigned int  cmd,
+						 unsigned long arg);
+
+static int corgibl_step_contrast_setting(int);
+
+static spinlock_t bl_lock = SPIN_LOCK_UNLOCKED;
+
+#ifdef CONFIG_PROC_FS
+struct proc_dir_entry *proc_bl;
+
+typedef struct _duty_vr_t {
+	int duty;
+	int vr;
+} duty_vr_t;
+
+#if defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD)
+static duty_vr_t corgibl_duty_table[CORGI_LIGHT_SETTING] = {
+	{0x00, 0},	//   0%		Light Off
+	{0x01, 0},	//  20%		Dim 1
+	{0x05, 0},	//  40%		2
+	{0x0b, 0},	//  70%		3
+	{0x05, 1},	//  40%		4
+	{0x0b, 1},	//  70%		5
+	{0x1f, 1}	// 100%		6
+};
+#else
+static duty_vr_t corgibl_duty_table[CORGI_LIGHT_SETTING] = {
+	{0x00, 0},	//   0%		Light Off
+	{0x01, 0},	//  20%		Dim
+	{0x02, 0},	//  25%		1
+	{0x0b, 0},	//  70%		2
+	{0x05, 1},	//  40%		3
+	{0x0b, 1},	//  70%		4
+	{0x1f, 1}	// 100%		5
+};
+#endif
+
+#define SetBacklightDuty(a)	ssp_put_dac_val(0x40 | ((a) & 0x1f), CS_LZ9JG18);
+#define SetBacklightVR(a)	if (a) {set_scoop_gpio(CORGI_SCP_BACKLIGHT_CONT);} else {reset_scoop_gpio(CORGI_SCP_BACKLIGHT_CONT);}
+
+static ssize_t corgibl_read_params(struct file *file, char *buf,
+								   size_t nbytes, loff_t *ppos)
+{
+	char outputbuf[15];
+	int count;
+	if (*ppos>0) /* Assume reading completed in previous read*/
+		return 0;
+	count = sprintf(outputbuf, "0x%02X%02X\n",
+					corgibl_duty_table[counter_step_contrast].vr,
+					corgibl_duty_table[counter_step_contrast].duty);
+	*ppos += count;
+	if (count>nbytes)	/* Assume output can be read at one time */
+		return -EINVAL;
+	if (copy_to_user(buf, outputbuf, count))
+		return -EFAULT;
+	return count;
+}
+
+static ssize_t corgibl_write_params(struct file *file, const char *buf,
+									size_t nbytes, loff_t *ppos)
+{
+	unsigned long		param;
+	char			*endp;
+	unsigned long flags;
+
+	param = simple_strtoul(buf,&endp,0);
+	SetBacklightDuty(param & 0xff);
+	SetBacklightVR((param & 0xff00) >> 8);
+	return nbytes+endp-buf;
+}
+
+static struct file_operations proc_params_operations = {
+	read:	corgibl_read_params,
+	write:	corgibl_write_params,
+};
+#endif
+
+void corgibl_blank(int blank)
+{
+	if (blank) {
+		if (!is_corgibl_blank) {
+			is_corgibl_blank = 1;
+			counter_step_save = counter_step_contrast;
+			corgibl_step_contrast_setting(0);
+		}
+	} else {
+		if (is_corgibl_blank && !is_corgibl_pm) {
+			corgibl_step_contrast_setting(counter_step_save);
+			is_corgibl_blank = 0;
+		}
+	}
+}
+
+
+int corgibl_pm_callback(struct pm_dev* pm_dev,
+							   pm_request_t req, void *data)
+{
+	switch (req) {
+	case PM_SUSPEND:
+		is_corgibl_pm = 1;
+		corgibl_blank(1);
+		break;
+	case PM_RESUME:
+		is_corgibl_pm = 0;
+		corgibl_blank(0);
+		break;
+	}
+	return 0;
+}
+
+static struct file_operations corgibl_fops = {
+	ioctl:		corgibl_ioctl,
+};
+
+static int corgibl_major;
+
+#define CHECK_BATTERY_TIME	1
+static int corgibl_step_contrast_setting(int need_value)
+{
+	int ac_in = 0;
+	unsigned long flags;
+	extern void sharpsl_kick_battery_check(int,int,int);
+
+	//sharpsl_kick_battery_check(0,1,0);	// check battery and wait 10msec
+
+	if (need_value < 0 ) need_value = 0;
+	if ( need_value > corgibl_limit )
+		need_value = corgibl_limit;
+
+	spin_lock_irqsave(&bl_lock, flags);
+	SetBacklightDuty(corgibl_duty_table[need_value].duty);
+	SetBacklightVR(corgibl_duty_table[need_value].vr);
+	spin_unlock_irqrestore(&bl_lock, flags);
+	counter_step_contrast = need_value;
+
+	//sharpsl_kick_battery_check(1,0,0);	// wait 10msec and check battery
+
+	return counter_step_contrast;
+}
+
+static int corgibl_step_contrast_setting_nocheck(int need_value)
+{
+	int ac_in = 0;
+	unsigned long flags;
+
+
+	if (need_value < 0 ) need_value = 0;
+	if ( need_value > corgibl_limit )
+		need_value = corgibl_limit;
+
+	spin_lock_irqsave(&bl_lock, flags);
+	SetBacklightDuty(corgibl_duty_table[need_value].duty);
+	SetBacklightVR(corgibl_duty_table[need_value].vr);
+	spin_unlock_irqrestore(&bl_lock, flags);
+
+	counter_step_contrast = need_value;
+
+	return counter_step_contrast;
+}
+
+
+static int	temporary_contrast_set_flag = 0;
+
+void corgibl_temporary_contrast_set(void)
+{
+	int need_value = counter_step_contrast;
+	unsigned long flags;
+
+	if (temporary_contrast_set_flag) {
+		return;
+	}
+	temporary_contrast_set_flag = 1;
+	corgibl_step_contrast_setting(need_value);
+}
+
+void corgibl_temporary_contrast_reset(void)
+{
+	int need_value = counter_step_contrast;
+	unsigned long flags;
+
+	if (!temporary_contrast_set_flag) {
+		return;
+	}
+	temporary_contrast_set_flag = 0;
+	corgibl_step_contrast_setting(need_value);
+}
+
+void corgibl_set_limit_contrast(int val)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&bl_lock, flags);
+	if ((val > CORGI_LIGHT_SETTING - 1) || (val < 0)) {
+		if (corgibl_limit != CORGI_LIGHT_SETTING - 1) {
+			printk("corgi_bl : unlimit contrast\n");
+		}
+		corgibl_limit = CORGI_LIGHT_SETTING - 1;
+	}
+	else {
+		if (corgibl_limit != val) {
+			printk("corgi_bl : change limit contrast %d\n", val);
+		}
+		corgibl_limit = val;
+	}
+	spin_unlock_irqrestore(&bl_lock, flags);
+	if (counter_step_contrast > corgibl_limit) {
+		corgibl_step_contrast_setting_nocheck(corgibl_limit);
+	}
+}
+
+static int corgibl_ioctl(struct inode* inode,
+						 struct file*  filp,
+						 unsigned int  cmd,
+						 unsigned long arg)
+{
+	int ret;
+
+	ret = (-EINVAL);
+	
+	switch(cmd) {
+	case CORGI_BL_IOCTL_ON:
+		ret = corgibl_step_contrast_setting(counter_step_contrast);
+		break;
+	case CORGI_BL_IOCTL_OFF:
+		ret = corgibl_step_contrast_setting(0);
+		break;
+	case CORGI_BL_IOCTL_STEP_CONTRAST:
+		ret = corgibl_step_contrast_setting(arg);
+		break;
+	case CORGI_BL_IOCTL_GET_STEP_CONTRAST:
+		ret = counter_step_contrast;
+		break;
+	case CORGI_BL_IOCTL_GET_STEP:
+		ret = CORGI_LIGHT_SETTING;
+		break;
+	default:
+		;
+	}
+	
+	return ret;
+}
+
+int __init corgibl_init(void)
+{
+	int result;
+
+	corgibl_major = BL_MAJOR;
+
+	result = register_chrdev(corgibl_major, BL_NAME, &corgibl_fops);
+
+	if (result < 0) {
+#ifdef DEBUG
+	  	printk(KERN_WARNING "corgibl: cant get major %d\n", 
+		       corgibl_major);
+#endif
+		return result;
+	}
+  
+	if (corgibl_major == 0) {
+	  	corgibl_major = result;
+	}
+
+	corgibl_step_contrast_setting(counter_step_contrast);
+
+#ifdef CONFIG_PROC_FS
+	{
+		struct proc_dir_entry *entry;
+
+		proc_bl = proc_mkdir("driver/fl", NULL);
+		if (proc_bl == NULL) {
+			corgibl_step_contrast_setting(0);
+			unregister_chrdev(corgibl_major, "corgi-bl");
+			printk(KERN_ERR "corgibl: can't create /proc/driver/fl\n");
+			return -ENOMEM;
+		}
+		entry = create_proc_entry("corgi-bl",
+								  S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH,
+								  proc_bl);
+		if (entry) {
+			entry->proc_fops = &proc_params_operations;
+		} else {
+			remove_proc_entry("driver/fl", &proc_root);
+			proc_bl = 0;
+			corgibl_step_contrast_setting(0);
+			unregister_chrdev(corgibl_major, "corgi-bl");
+			printk(KERN_ERR "corgibl: can't create /proc/driver/fl/\n");
+			return -ENOMEM;
+		}
+	}
+#endif
+
+	printk("Backlight Driver Initialized.\n");
+  
+	return 0;
+}
+
+#ifdef MODULE
+void __exit corgibl_exit(void)
+{
+	corgibl_step_contrast_setting(0);
+
+	unregister_chrdev(corgibl_major, "corgi-bl");
+
+#ifdef CONFIG_PROC_FS
+	{
+		remove_proc_entry("corgi-bl", proc_bl);
+		remove_proc_entry("driver/fl", NULL);
+		proc_bl = 0;
+	}
+#endif
+	printk("Backlight Driver Unloaded\n");
+}
+#endif
+
+module_init(corgibl_init);
+#ifdef MODULE
+module_exit(corgibl_exit);
+#endif
--- /dev/null
+++ linux-2.6.10-rc1/drivers/video/w100fb.c
@@ -0,0 +1,3591 @@
+/*
+ * linux/drivers/video/w100fb.c
+ *
+ * Frame Buffer Device for ATI w100 (Wallaby)
+ *
+ * Copyright (C) 2002, ATI Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Based on:
+ *  drivers/video/skeletonfb.c
+ *
+ * ChangeLog:
+ *  28-02-2003 SHARP supported VRAM image cache for ver.1.3
+ *  19-03-2003 SHARP disabled VRAM image cache for ver.1.3
+ *  16-04-2003 SHARP for Shepherd
+ */
+
+// define this here because unistd.h needs it
+extern int errno;
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/uaccess.h>
+// unistd.h is included for the configuration ioctl stuff
+#define __KERNEL_SYSCALLS__ 1
+#include <asm/unistd.h>
+#undef  __KERNEL_SYSCALLS__
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/tty.h>
+#include <linux/fs.h>
+#include <linux/file.h>
+
+#include "w100fb.h"
+#include <linux/pm.h>
+
+//#define _IMAGE_CACHE_SUPPORT // for image cache on video memory
+//#define CONFIG_FBCON_ROTATE_R 1
+
+#ifdef CONFIG_PM
+#include <asm/arch-pxa/corgi.h>
+static struct pm_dev *w100fb_pm_dev;
+static int w100fb_pm_callback(struct pm_dev* pm_dev,pm_request_t req, void* data);
+#endif //CONFIG_PM
+
+static void w100fb_pm_suspend(int suspend_mode);
+static void w100fb_pm_resume(int resume_mode);
+
+#define W100FB_SUSPEND_EXTMEM 0
+#define W100FB_SUSPEND_ALL    1 
+
+static void w100fb_resume(void);
+static void w100fb_suspend(u32 mode);
+static void w100fb_init_qvga_rotation(u16 deg);
+static void w100fb_soft_reset(void);
+static void w100fb_clear_screen(u32 mode,void *fbuf);
+static void w100fb_vsync(void);
+
+static void lcdtg_hw_init(u32 mode);
+static void lcdtg_lcd_change(u32 mode);
+static void lcdtg_resume(void);
+static void lcdtg_suspend(void);
+static void lcdtg_i2c_start_sequence(u8 base_data);
+static void lcdtg_i2c_stop_sequence(u8 base_data);
+static void lcdtg_i2c_wait_ack(u8 base_data);
+
+#define USE_XTAL_12_5     1    // if not defined, it is assumed to be 14.3MHz
+
+// Some hardware related constants
+// The name the kernel will know us by
+#define W100FB_NAME         "W100FB"
+
+// Physical addresses, offsets & lengths
+#define REG_OFFSET        0x10000
+#define FB_OFFSET         MEM_EXT_BASE_VALUE
+#define W100FB_PHYS_ADDRESS 0x08000000
+#define W100FB_REG_BASE     (W100FB_PHYS_ADDRESS+REG_OFFSET)
+#define W100FB_FB_BASE      (W100FB_PHYS_ADDRESS+MEM_EXT_BASE_VALUE)
+#ifdef _IMAGE_CACHE_SUPPORT
+#define REMAPPED_FB_LEN   0x200000
+#else //_IMAGE_CACHE_SUPPORT
+#define REMAPPED_FB_LEN   0x15ffff
+#endif //_IMAGE_CACHE_SUPPORT
+#define REMAPPED_CFG_LEN  0x10
+#define REMAPPED_MMR_LEN  0x2000
+#define W100FB_PHYS_ADR_LEN 0x1000000
+#define MAX_XRES          480
+#define MAX_YRES          640
+#define BITS_PER_PIXEL    16
+
+// Pseudo palette size
+#define MAX_PALETTES      16
+
+// ioctls
+#define W100FB_CONFIG          0x57415200 /* WAL\00 */
+#define W100INIT_ITEM          0
+#define W100INIT_ALL           1
+#define W100INIT_ITEM_WITH_VAL 2
+
+#define W100FB_POWERDOWN       0x57415201 /* WAL\01 */
+#define W100FB_CONFIG_EX       0x57415202 /* WAL\02 */
+
+// General frame buffer data structures
+static struct fb_info info;
+
+struct w100fb_par {
+  u32 xres;
+  u32 yres;
+  u32 xres_virtual;
+  u32 yres_virtual;
+
+  u32 bits_per_pixel;
+
+  u32 visual;
+  u32 palette_size;
+};
+
+/*static struct w100fb_info fb_info.;*/
+static struct w100fb_par current_par;
+static int pseudo_pal[MAX_PALETTES];
+
+
+typedef struct _W100CONFIG_ARGS_
+{
+  int  arg_count;
+  char config_filename[256];
+  char section_name[64];
+  char item_name[64];
+  unsigned int supplied_value;
+} W100CONFIG_ARGS;
+
+
+// Remapped addresses for base cfg, memmapped regs and the frame buffer itself
+static void *remapped_base;
+static void *remapped_regs;
+static void *remapped_fbuf;
+
+static int isRemapped = 0;
+
+// for resolution change
+#define LCD_MODE_480    0
+#define LCD_MODE_320    1
+#define LCD_MODE_240    2
+#define LCD_MODE_UNKNOWN (-1)
+
+int w100fb_lcdMode = LCD_MODE_UNKNOWN; //default UNKNOWN
+
+static u16 *gSaveImagePtr[640] = {NULL};
+#define SAVE_IMAGE_MAX_SIZE ((640 * 480 * BITS_PER_PIXEL) / 8)
+
+#ifdef _IMAGE_CACHE_SUPPORT // for image cache on video memory
+
+#define IMG_CACHE_MALLOC_SIZE 0x1000
+#define IMG_CACHE_OFFSET_VGA (0x97008)
+#define IMG_CACHE_TOTAL_SIZE_VGA (0x200000-0x4000-IMG_CACHE_OFFSET_VGA)
+#define IMG_CACHE_SKIP_MARK (0xffffffff)
+
+static u32 *save_img_cache_ptr=NULL;
+static u32 save_img_alloc_num=0;
+#define __PRINTK(arg...) //printk(arg)
+#undef __SUM //for debug
+
+static u32* save_image_cache(u32 *alloc_num);
+static int restore_image_cache(u32 *img_src,u32 alloc_num);
+static int cleanup_image_cache(u32 *img_src,u32 alloc_num);
+
+// defalut don't skip
+static int start_skip_save_image_no = (-1);
+static int end_skip_save_image_no = (-1);
+#endif //_IMAGE_CACHE_SUPPORT
+
+int w100fb_isblank = 0;
+
+static int fb_blank_normal = 0;
+static int isSuspended_tg_only = 0;
+
+#if defined(CONFIG_ARCH_SHARP_SL)
+// checking in mm/omm_kill.c
+int disable_signal_to_mm = 0;
+#endif
+
+int w100fb_init(void);
+int w100fb_setup(char*);
+static int w100fb_ioctl(struct inode *inode, 
+			struct file *file, 
+			unsigned int cmd,
+			unsigned long arg,
+			struct fb_info *info);
+void w100fb_init_from_hwtab(int mode, int fd, char *section, char *item, u32 val);
+
+int isspace(int x);
+int config_open(const char *config_filename);
+int config_close(int config_fd);
+int config_get_dword(int config_fd,
+		     const char *section,
+		     const char *id,
+		     u32 *val,
+		     u32 defval);
+long my_strtol(const char *string, char **endPtr, int base);
+
+
+#define LCD_SHARP_QVGA 0
+#define LCD_SHARP_VGA  1
+static void w100fb_init_sharp_lcd(u32 mode);
+static void w100fb_PwmSetup(void);
+static void w100fb_InitExtMem(u32 mode);
+
+/* ------------------- chipset specific functions -------------------------- */
+
+//
+// Initialize gamma to the middle of the contrast range. Even though
+// the ATI core lib eventually sets the gamma, this will allow things
+// like X to work properly
+//
+void w100fb_gamma_init(void)
+{
+  video_ctrl_u   video_ctrl;
+  gamma_slope_u  gamma_slope;
+  gamma_value1_u gamma_value1;
+  gamma_value2_u gamma_value2;
+
+#if 1  // use default value
+	return;
+#endif
+
+  // For RGB gamma correction
+  gamma_slope.f.slope1  = 0;
+  gamma_slope.f.slope2  = 0;
+  gamma_slope.f.slope3  = 0;
+  gamma_slope.f.slope4  = 0;
+  gamma_slope.f.slope5  = 0;
+  gamma_slope.f.slope6  = 0;
+  gamma_slope.f.slope7  = 0;
+  gamma_slope.f.slope8  = 0;
+  gamma_value1.f.gamma1 = 0;
+  gamma_value1.f.gamma2 = 41;
+  gamma_value1.f.gamma3 = 82;
+  gamma_value1.f.gamma4 = 123;
+  gamma_value2.f.gamma5 = 156;
+  gamma_value2.f.gamma6 = 181;
+  gamma_value2.f.gamma7 = 206;
+  gamma_value2.f.gamma8 = 231;
+
+  // Correct graphic & video on RGB
+  video_ctrl.f.rgb_gamma_sel = 3;
+
+  // For Y gamma correction
+  video_ctrl.f.gamma_sel = 0;
+
+  writel((u32)(gamma_value1.val), remapped_regs+mmGAMMA_VALUE1);
+  writel((u32)(gamma_value2.val), remapped_regs+mmGAMMA_VALUE2);
+  writel((u32)(gamma_slope.val), remapped_regs+mmGAMMA_SLOPE);
+  writel((u32)(video_ctrl.val), remapped_regs+mmVIDEO_CTRL);
+}
+
+//
+// Initialization of critical w100 hardware
+//
+static void w100fb_hw_init(void)
+{
+  u32                   temp32;
+  cif_cntl_u            cif_cntl;
+  intf_cntl_u		intf_cntl;
+  cfgreg_base_u         cfgreg_base;
+  wrap_top_dir_u        wrap_top_dir;
+  cif_read_dbg_u	cif_read_dbg;
+  cpu_defaults_u	cpu_default;
+  cif_write_dbg_u       cif_write_dbg;
+  wrap_start_dir_u      wrap_start_dir;
+  mc_ext_mem_location_u mc_ext_mem_loc;
+  cif_io_u              cif_io;
+
+  if(isRemapped == 0){
+      // Request the memory region we want
+      request_mem_region(W100FB_PHYS_ADDRESS, W100FB_PHYS_ADR_LEN, "W100FB_BASE"); 
+
+      // remap the areas we're going to use
+      remapped_base = ioremap_nocache(W100FB_PHYS_ADDRESS, REMAPPED_CFG_LEN);
+      remapped_regs = ioremap_nocache(W100FB_REG_BASE, REMAPPED_MMR_LEN);
+      remapped_fbuf = ioremap_nocache(W100FB_FB_BASE, REMAPPED_FB_LEN);
+
+      isRemapped = 1;
+  }
+
+  w100fb_soft_reset();
+
+  // This is what the fpga_init code does on reset. May be wrong
+  // but there is little info available
+  writel(0x31, remapped_regs+mmSCRATCH_UMSK);
+  for (temp32 = 0; temp32 < 10000; temp32++)
+    readl(remapped_regs+mmSCRATCH_UMSK);
+  writel(0x30, remapped_regs+mmSCRATCH_UMSK);
+
+  // Set up CIF
+  cif_io.val = defCIF_IO;
+  writel((u32)(cif_io.val), remapped_regs+mmCIF_IO);
+
+  cif_write_dbg.val = readl(remapped_regs+mmCIF_WRITE_DBG);
+  cif_write_dbg.f.dis_packer_ful_during_rbbm_timeout = 0;
+  cif_write_dbg.f.en_dword_split_to_rbbm = 1;
+  cif_write_dbg.f.dis_timeout_during_rbbm = 1;
+  writel((u32)(cif_write_dbg.val), remapped_regs+mmCIF_WRITE_DBG);
+
+  cif_read_dbg.val = readl(remapped_regs+mmCIF_READ_DBG);
+  cif_read_dbg.f.dis_rd_same_byte_to_trig_fetch = 1;
+  writel((u32)(cif_read_dbg.val), remapped_regs+mmCIF_READ_DBG);
+
+  cif_cntl.val = readl(remapped_regs+mmCIF_CNTL);
+  cif_cntl.f.dis_system_bits = 1;
+  cif_cntl.f.dis_mr = 1;
+  cif_cntl.f.en_wait_to_compensate_dq_prop_dly = 0;
+  cif_cntl.f.intb_oe = 1;
+  cif_cntl.f.interrupt_active_high = 1;
+  writel((u32)(cif_cntl.val), remapped_regs+mmCIF_CNTL);
+
+  // Setup cfgINTF_CNTL and cfgCPU defaults
+  intf_cntl.val = defINTF_CNTL;
+  intf_cntl.f.ad_inc_a = 1;
+  intf_cntl.f.ad_inc_b = 1;
+  intf_cntl.f.rd_data_rdy_a = 0;
+  intf_cntl.f.rd_data_rdy_b = 0;
+  writeb((u8)(intf_cntl.val), remapped_base+cfgINTF_CNTL);
+
+  cpu_default.val = defCPU_DEFAULTS;
+  cpu_default.f.access_ind_addr_a = 1;
+  cpu_default.f.access_ind_addr_b = 1;
+  cpu_default.f.access_scratch_reg = 1;
+  cpu_default.f.transition_size = 0;
+  writeb((u8)(cpu_default.val), remapped_base+cfgCPU_DEFAULTS);
+
+  // set up the apertures
+  writeb((u8)(REG_BASE_VALUE >> 16), remapped_base+cfgREG_BASE);
+
+  cfgreg_base.val = defCFGREG_BASE;
+  cfgreg_base.f.cfgreg_base = CFG_BASE_VALUE;
+  writel((u32)(cfgreg_base.val), remapped_regs+mmCFGREG_BASE);
+
+  // This location is relative to internal w100 addresses
+  writel(0x15FF1000, remapped_regs+mmMC_FB_LOCATION);
+
+  mc_ext_mem_loc.val = defMC_EXT_MEM_LOCATION;
+  mc_ext_mem_loc.f.mc_ext_mem_start = MEM_EXT_BASE_VALUE>>8;
+  mc_ext_mem_loc.f.mc_ext_mem_top = MEM_EXT_TOP_VALUE>>8;
+  writel((u32)(mc_ext_mem_loc.val), remapped_regs+mmMC_EXT_MEM_LOCATION);
+
+  if (w100fb_lcdMode == LCD_MODE_UNKNOWN){
+      w100fb_InitExtMem(LCD_SHARP_VGA);
+  } else if(w100fb_lcdMode == LCD_MODE_480) {
+      w100fb_InitExtMem(LCD_SHARP_VGA);
+  } else {
+      w100fb_InitExtMem(LCD_SHARP_QVGA);
+  }
+
+  wrap_start_dir.val = defWRAP_START_DIR;
+  wrap_start_dir.f.start_addr = WRAP_BUF_BASE_VALUE>>1;
+  writel((u32)(wrap_start_dir.val), remapped_regs+mmWRAP_START_DIR);
+
+  wrap_top_dir.val = defWRAP_TOP_DIR;
+  wrap_top_dir.f.top_addr = WRAP_BUF_TOP_VALUE>>1;
+  writel((u32)(wrap_top_dir.val), remapped_regs+mmWRAP_TOP_DIR);
+
+  writel((u32)0x2440, remapped_regs+mmRBBM_CNTL);
+}
+
+
+//
+// Set a single color register. N/A on W100
+//
+static int w100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+		   u_int trans, struct fb_info *info)
+{
+	unsigned int val;
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (info->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+					7471 * blue) >> 16;
+
+	switch (info->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 12 or 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno <= MAX_PALETTES) {
+			
+			u32 *pal = info->pseudo_palette;
+
+			val = (red & 0xf800) | ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
+
+			pal[regno] = val;
+			ret = 0;
+		}
+		break;
+
+	}
+
+	return ret;
+}
+
+
+
+//
+// Pan the display based on var->xoffset & var->yoffset values
+//
+static int w100fb_pan_display(struct fb_var_screeninfo *var,
+			     struct fb_info *info)			     
+{
+
+  return 0;
+}
+
+//
+// Blank the display based on value in blank_mode
+//
+static int w100fb_blank(int blank_mode, struct fb_info *info)
+{
+    if(!w100fb_isblank && !in_interrupt()){
+	if(blank_mode && fb_blank_normal == 0){
+	    w100fb_pm_suspend( 1 );
+	    fb_blank_normal = blank_mode;
+	}else if(!blank_mode && fb_blank_normal != 0){
+	    w100fb_pm_resume( 1 );
+	    fb_blank_normal = blank_mode;
+	}
+    }
+
+    return 0;
+}
+
+//
+// Set up the display for the fb subsystem
+//
+static void w100fb_activate_var(struct fb_info *info)
+{
+  u32 temp32;
+  int isInitTG = 0;
+  struct fb_var_screeninfo *var = &info->var;
+
+  // Set the hardware to 565
+  temp32 = readl(remapped_regs+mmDISP_DEBUG2);
+  temp32 &= 0xff7fffff;
+  temp32 |= 0x00800000;
+  writel(temp32, remapped_regs+mmDISP_DEBUG2);
+
+#ifdef _IMAGE_CACHE_SUPPORT // FOR RESOLUTION CHANGE
+  // VGA only
+  if(LCD_MODE_480 == w100fb_lcdMode){
+    __PRINTK("RESOLUTION CHANGE: save image cache ... ");
+
+    if(save_img_cache_ptr || save_img_alloc_num){
+      __PRINTK("ERROR!\n");
+    }else{
+      save_img_cache_ptr = save_image_cache(&save_img_alloc_num);
+
+      if(save_img_cache_ptr && save_img_alloc_num){
+	__PRINTK("SUCCESS!\n");
+      }else{
+	__PRINTK("ERROR!!\n");
+      }
+    }
+  }
+#endif //_IMAGE_CACHE_SUPPORT
+
+  switch(w100fb_lcdMode){
+  case LCD_MODE_480:
+      if(var->xres == 320 && var->yres == 240){
+
+	  printk("change resolution 480x640 => 320x240\n");
+
+	  w100fb_PwmSetup();
+	  w100fb_vsync();
+	  w100fb_suspend(W100FB_SUSPEND_EXTMEM);
+	  w100fb_init_sharp_lcd(LCD_SHARP_QVGA);
+	  w100fb_init_qvga_rotation( (u16)270 );
+	  w100fb_InitExtMem(LCD_SHARP_QVGA);
+	  w100fb_clear_screen(LCD_SHARP_QVGA,NULL);
+	  lcdtg_lcd_change(LCD_SHARP_QVGA);
+
+	  w100fb_lcdMode = LCD_MODE_320;
+
+      }else if(var->xres == 240 && var->yres == 320){
+
+	  printk("change resolution 480x640 => 240x320\n");
+
+	  w100fb_PwmSetup();
+	  w100fb_vsync();
+	  w100fb_suspend(W100FB_SUSPEND_EXTMEM);
+	  w100fb_init_sharp_lcd(LCD_SHARP_QVGA);
+	  w100fb_init_qvga_rotation( (u16)0 );
+	  w100fb_InitExtMem(LCD_SHARP_QVGA);
+  	  w100fb_clear_screen(LCD_SHARP_QVGA,NULL);
+	  lcdtg_lcd_change(LCD_SHARP_QVGA);
+
+	  w100fb_lcdMode = LCD_MODE_240;
+
+      }
+      break;
+  case LCD_MODE_240:
+      if(var->xres == 480 && var->yres == 640){
+
+	  printk("change resolution 240x320 => 480x640\n");
+
+	  w100fb_PwmSetup();
+	  w100fb_clear_screen(LCD_SHARP_QVGA,NULL);
+	  writel(0xBFFFA000, remapped_regs+mmMC_EXT_MEM_LOCATION);
+	  w100fb_InitExtMem(LCD_SHARP_VGA);
+	  w100fb_clear_screen(LCD_SHARP_VGA,(void*)0xF1A00000);
+	  w100fb_vsync();
+	  w100fb_init_sharp_lcd(LCD_SHARP_VGA);
+	  lcdtg_lcd_change(LCD_SHARP_VGA);
+
+	  w100fb_lcdMode = LCD_MODE_480;
+
+      }else if(var->xres == 320 && var->yres == 240){
+
+	  printk("change resolution 240x320 => 320x240\n");
+
+  	  w100fb_clear_screen(LCD_SHARP_QVGA,NULL);
+	  w100fb_init_qvga_rotation( (u16)270 );
+
+	  w100fb_lcdMode = LCD_MODE_320;
+      }
+      break;
+  case LCD_MODE_320:
+      if(var->xres == 480 && var->yres == 640){
+
+	  printk("change resolution 320x240 => 480x640\n");
+
+	  w100fb_PwmSetup();
+	  w100fb_clear_screen(LCD_SHARP_QVGA,NULL);
+	  writel(0xBFFFA000, remapped_regs+mmMC_EXT_MEM_LOCATION);
+	  w100fb_InitExtMem(LCD_SHARP_VGA);
+	  w100fb_clear_screen(LCD_SHARP_VGA,(void*)0xF1A00000);
+	  w100fb_vsync();
+	  w100fb_init_sharp_lcd(LCD_SHARP_VGA);
+	  lcdtg_lcd_change(LCD_SHARP_VGA);
+
+	  w100fb_lcdMode = LCD_MODE_480;
+
+      }else if(var->xres == 240 && var->yres == 320){
+
+	  printk("change resolution 320x240 => 240x320\n");
+
+  	  w100fb_clear_screen(LCD_SHARP_QVGA,NULL);
+	  w100fb_init_qvga_rotation( (u16)0 );
+
+	  w100fb_lcdMode = LCD_MODE_240;
+      }
+      break;
+  case LCD_MODE_UNKNOWN:
+      printk("reset resolution unknown => 480x640\n");
+      w100fb_init_sharp_lcd(LCD_SHARP_VGA);
+      w100fb_lcdMode = LCD_MODE_480;
+      isInitTG = 1;
+      break;
+  default:
+      printk("resolution error !!! \n");
+      break;
+  }
+
+#ifdef _IMAGE_CACHE_SUPPORT // FOR RESOLUTION CHANGE
+  if(LCD_MODE_480 == w100fb_lcdMode){
+
+    __PRINTK("RESOLUTION CHANGE: restore image cache ... ");
+    if(save_img_cache_ptr != NULL &&
+       save_img_alloc_num != 0){
+
+      if(!restore_image_cache(save_img_cache_ptr,save_img_alloc_num)){
+	save_img_cache_ptr = NULL;
+	save_img_alloc_num = 0;
+	__PRINTK("SUCCESS!\n");
+      }else{
+	__PRINTK("ERROR!!\n");
+      }
+
+    }else{
+      __PRINTK("ERROR!\n");
+    }
+  }
+#endif //_IMAGE_CACHE_SUPPORT
+
+  // Set the initial contrast to something sane
+  w100fb_gamma_init();
+
+  // Do the rest of the display initialization
+
+  switch(w100fb_lcdMode){
+  case LCD_MODE_480:
+      if(isInitTG != 0)
+	  lcdtg_hw_init(LCD_SHARP_VGA);
+      break;
+  case LCD_MODE_240:
+  case LCD_MODE_320:
+      if(isInitTG != 0)
+	  lcdtg_hw_init(LCD_SHARP_QVGA);
+      break;
+  default:
+      printk("resolution error !!! \n");
+      break;
+  }
+}
+
+/*
+ *  w100fb_check_var():
+ *    Get the video params out of 'var'. If a value doesn't fit, round it up,
+ *    if it's too big, return -EINVAL.
+ *
+ *    Round up in the following order: bits_per_pixel, xres,
+ *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
+ *    bitfields, horizontal timing, vertical timing.
+ */
+static int w100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	
+	
+  	if(!((var->xres == 480 && var->yres == 640)||
+     		(var->xres == 320 && var->yres == 240)||
+     		(var->xres == 240 && var->yres == 320))) 
+     		{
+      			var->xres = MAX_XRES;
+      			var->yres = MAX_YRES;
+  	}
+	var->xres_virtual =
+		max(var->xres_virtual, var->xres);
+	var->yres_virtual =
+		max(var->yres_virtual, var->yres);
+
+	var->bits_per_pixel = BITS_PER_PIXEL;
+
+//	if ( var->bits_per_pixel == 16 ) {
+		var->red.offset   = 11; var->red.length   = 5;
+		var->green.offset = 5;  var->green.length = 6;
+		var->blue.offset  = 0;  var->blue.length  = 5;
+		var->transp.offset = var->transp.length = 0;
+//	} else {
+//		var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
+//		var->red.length   = 8;
+//		var->green.length = 8;
+//		var->blue.length  = 8;
+//		var->transp.length = 0;
+//	}
+
+  	var->red.msb_right = 0;
+  	var->green.msb_right = 0;
+  	var->blue.msb_right = 0;
+  	var->transp.msb_right = 0;
+  	var->nonstd = 0;
+	var->grayscale = 0;
+	//var->rotate = 90;
+  	
+	return 0;
+}
+
+/*
+ * w100fb_set_par():
+ *	Set the user defined part of the display for the specified console
+ *      by looking at the values in info.var
+ */
+static int w100fb_set_par(struct fb_info *info)
+{
+ 	current_par.xres=info->var.xres;
+  	current_par.yres=info->var.yres;
+  //current_par.xres_virtual=var->xres_virtual;
+  //current_par.yres_virtual=var->xres_virtual;
+  //current_par.bits_per_pixel=var->;
+  //current_par.visual=var->;
+  //current_par.palette_size=var->;
+  
+  	printk(KERN_INFO "W100: xres: %d yres: %d bbp: %d mode: %d\n", info->var.xres,info->var.yres,info->var.bits_per_pixel,w100fb_lcdMode);
+
+
+
+  	if (info->var.bits_per_pixel == 1)
+  	{
+    		info->fix.visual = FB_VISUAL_MONO10;
+  	}
+  	else if (info->var.bits_per_pixel <= 8) 
+  	{
+    		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+  	}
+  	else
+  	{
+    		info->fix.visual = FB_VISUAL_TRUECOLOR;
+  	}
+  	
+#if defined(CONFIG_FBCON_ROTATE_R) || defined(CONFIG_FBCON_ROTATE_L)
+	info->fix.xpanstep       = 0;
+	info->fix.xwrapstep      = 0;
+#else
+	info->fix.ypanstep       = 0;
+	info->fix.ywrapstep      = 0;
+#endif
+
+
+  	w100fb_activate_var(info);
+
+  	if(w100fb_lcdMode == LCD_MODE_UNKNOWN || w100fb_lcdMode == LCD_MODE_480){
+      		info->fix.line_length = (480 * BITS_PER_PIXEL) / 8;
+      		info->fix.smem_len = 0x200000;
+  	} else if(w100fb_lcdMode == LCD_MODE_320){
+      		info->fix.line_length = (320 * BITS_PER_PIXEL) / 8;
+      		info->fix.smem_len = 0x60000;
+  	} else if(w100fb_lcdMode == LCD_MODE_240){
+      		info->fix.line_length = (240 * BITS_PER_PIXEL) / 8;
+      		info->fix.smem_len = 0x60000;
+  	}
+	//fbi->fb.fix.line_length = var->xres_virtual *
+	//			  var->bits_per_pixel / 8;
+	//fbi->fb.fix.smem_len		= fbi->max_xres * fbi->max_yres *
+	//				  fbi->max_bpp / 8;
+
+// FIXME
+// unsigned long palette_mem_size;
+//	fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
+
+//	palette_mem_size = fbi->palette_size * sizeof(u16);
+
+//	DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
+
+//	fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
+//	fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
+
+	printk(KERN_INFO "W100: xres: %d yres: %d bbp: %d mode: %d\n", info->var.xres,info->var.yres,info->var.bits_per_pixel,w100fb_lcdMode);
+
+	return 0;
+}
+
+
+//    
+//      Frame buffer operations
+//
+
+static struct fb_ops w100fb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_check_var	= w100fb_check_var,
+	.fb_set_par	= w100fb_set_par,	
+	.fb_setcolreg	= w100fb_setcolreg,
+	.fb_blank	= w100fb_blank,
+	.fb_pan_display	= w100fb_pan_display,	
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+	.fb_imageblit	= cfb_imageblit,
+	.fb_cursor	= soft_cursor,
+	/*.fb_rotate	= w100fb_rotate,*/
+	.fb_ioctl	= w100fb_ioctl,
+};
+
+int __init w100fb_setup(char *str)
+{
+  return 0;
+}
+
+int __init w100fb_init(void)
+{
+	int retval;
+
+	corgibl_init();
+
+  	w100fb_lcdMode = LCD_MODE_UNKNOWN;
+  
+  	w100fb_hw_init();
+	w100fb_PwmSetup();
+
+  /*w100fb_encode_var(&default_var, NULL, NULL);FIXME*/
+  
+  /*info.disp = &disp;FIXME*/
+  
+  /* info.par = current_par; */
+  
+	info.pseudo_palette = pseudo_pal;
+
+  	info.screen_base = remapped_fbuf;	
+
+	info.fbops		= &w100fb_ops;
+	info.flags		= FBINFO_FLAG_DEFAULT;
+	info.node		= -1;
+	info.currcon		= -1;
+
+	info.var.xres = MAX_XRES;
+  	info.var.xres_virtual = info.var.xres;
+  	info.var.yres = MAX_YRES;
+  	info.var.yres_virtual = info.var.yres;
+  	info.var.bits_per_pixel = BITS_PER_PIXEL;
+  	info.var.pixclock = 0x04; // 171521;
+
+//	info.var.hsync_len		= inf->hsync_len;
+//	info.var.left_margin		= inf->left_margin;
+//	info.var.right_margin	= inf->right_margin;
+//	info.var.vsync_len		= inf->vsync_len;
+//	info.var.upper_margin	= inf->upper_margin;
+//	info.var.lower_margin	= inf->lower_margin;
+	info.var.sync = 0;
+	info.var.grayscale = 0;
+
+
+  	info.var.red.offset = 11;
+  	info.var.red.length = 5;
+  	info.var.green.offset = 5;
+	info.var.green.length = 6;
+  	info.var.blue.offset = 0;
+  	info.var.blue.length = 5;
+  	info.var.transp.offset = 0;
+  	info.var.transp.length = 0;
+  	info.var.red.msb_right = 0;
+  	info.var.green.msb_right = 0;
+  	info.var.blue.msb_right = 0;
+  	info.var.transp.msb_right = 0;
+  	info.var.nonstd = 0;
+  	//info.var.rotate = 90;
+  
+  	info.var.xoffset = info.var.yoffset = 0;
+  	info.var.activate = FB_ACTIVATE_NOW;
+  	info.var.height = -1;
+  	info.var.width = -1;
+  	info.var.accel_flags	= 0;
+  	info.var.vmode = FB_VMODE_NONINTERLACED;
+  
+  /* info.fix = xxxfb_fix; FIXME */
+  	strcpy(info.fix.id, W100FB_NAME);
+	info.fix.type	= FB_TYPE_PACKED_PIXELS;
+	info.fix.type_aux	= 0;
+#if defined(CONFIG_FBCON_ROTATE_R) || defined(CONFIG_FBCON_ROTATE_L)
+	info.fix.xpanstep       = 0;
+	info.fix.xwrapstep      = 0;
+#else
+	info.fix.ypanstep       = 0;
+	info.fix.ywrapstep      = 0;
+#endif
+	
+	
+	info.fix.accel	= FB_ACCEL_NONE;
+	info.fix.smem_start = W100FB_FB_BASE;
+	info.fix.smem_len		= info.var.xres * info.var.yres *
+					  info.var.bits_per_pixel / 8;
+  	info.fix.mmio_start = W100FB_REG_BASE;
+  	info.fix.mmio_len = REMAPPED_MMR_LEN;
+  	info.fix.accel = FB_ACCEL_NONE;
+  
+  
+	w100fb_check_var(&info.var, &info);
+	w100fb_set_par(&info);
+  
+    retval = fb_find_mode(&info.var, &info, "480x640@60", NULL, 0, NULL, 16);
+  
+    if (!retval || retval == 4)
+	return -EINVAL;		
+  
+
+ // if (disp.var.bits_per_pixel > 1) 
+   // fbgen_install_cmap(0, &fb_info.gen);
+    
+  fb_alloc_cmap(&info.cmap, MAX_PALETTES*16, 0); //FIXME
+
+  if (register_framebuffer(&info) < 0)
+    return -EINVAL;
+
+#ifdef CONFIG_PM
+  w100fb_pm_dev = pm_register(PM_SYS_DEV, 0, w100fb_pm_callback);
+#endif //CONFIG_PM
+
+    printk(KERN_INFO "fb%d: %s frame buffer device\n", info.node,
+	   info.fix.id);	 
+  return 0;
+}
+
+void w100fb_cleanup()
+{
+  unregister_framebuffer(&info);
+
+  iounmap(remapped_base);
+  iounmap(remapped_regs);
+  iounmap(remapped_fbuf);
+  release_mem_region(W100FB_PHYS_ADDRESS, 0x1000000);
+
+  if(gSaveImagePtr[0] != NULL){
+	  int i;
+	  for (i = 0; i < 640; i++) {
+		  if (gSaveImagePtr[i] != NULL) {
+			  kfree(gSaveImagePtr[i]);
+			  gSaveImagePtr[i]=NULL;
+		  }
+	  }
+  }
+  isRemapped = 0;
+
+#ifdef _IMAGE_CACHE_SUPPORT //FOR CLEANUP
+  cleanup_image_cache(save_img_cache_ptr,
+		      save_img_alloc_num);
+  save_img_cache_ptr = NULL;
+  save_img_alloc_num = 0;
+#endif //_IMAGE_CACHE_SUPPORT
+}
+
+
+
+static int w100fb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+		       unsigned long arg, struct fb_info *info2)
+{
+  int fd;
+  W100CONFIG_ARGS *args = (W100CONFIG_ARGS *)arg;
+
+  switch (cmd)
+  {
+  case W100FB_CONFIG:
+    fd = config_open((char *)args->config_filename);
+    if (fd >= 0)
+    {
+      if (args->arg_count == 3)
+      {
+	w100fb_init_from_hwtab(W100INIT_ITEM,
+			     fd,
+			     (char *)args->section_name,
+			     (char *)args->item_name, 0);
+      }
+      else if (args->arg_count == 4)
+      {
+	w100fb_init_from_hwtab(W100INIT_ITEM_WITH_VAL,
+			     fd,
+			     (char *)args->section_name,
+			     (char *)args->item_name,
+			     (u32)args->supplied_value);
+      }
+      else
+      {
+	w100fb_init_from_hwtab(W100INIT_ALL, fd, NULL, NULL, 0);
+      }
+      config_close(fd);
+    }
+    else
+    {
+      printk("w100fb_ioctl: could not open hwtbl. fd = %x\n", fd);
+    }
+    break;
+  case W100FB_POWERDOWN:
+  {
+      int blank_mode = (int)arg;
+
+      if (blank_mode && !w100fb_isblank) {
+	  w100fb_pm_suspend( 0 );
+	  fb_blank_normal = 0;
+	  w100fb_isblank = blank_mode;
+      }
+      else if (!blank_mode && w100fb_isblank) {
+	  w100fb_pm_resume( 0 );
+	  fb_blank_normal = 0;
+	  w100fb_isblank = blank_mode;
+      }
+  }
+  break;
+
+#if defined(CONFIG_ARCH_SHARP_SL)
+  case W100FB_CONFIG_EX:
+    {
+      int *setup_arg = (int*)arg;
+      int mode;
+
+      // a)arg = NULL: check this ioctl.
+      // b)arg[0] = 0: disable memory check (disable signal).
+      // c)arg[0] = 1: enable memory check (enable signal).
+      // d)arg[0] = 2: set image cache info.
+      if(setup_arg == NULL)
+	return 0;
+
+      mode = setup_arg[0];
+      switch(mode){
+      case 0:
+	if(disable_signal_to_mm == 0){
+
+	  //printk("[w100fb] set the image cache info!\n");
+
+	  // disable memory check
+	  disable_signal_to_mm = 1;
+
+	  return 0;
+	}
+	break;
+      case 1:
+	if(disable_signal_to_mm == 1){
+
+	  //printk("[w100fb] reset the image cache info!\n");
+
+	  // enable memory check
+	  disable_signal_to_mm = 0;
+	  return 0;
+
+	}
+	break;
+#ifdef _IMAGE_CACHE_SUPPORT
+      case 2:
+	{
+	  u32 start,end;
+	  start = (u32)setup_arg[1];
+	  end = (u32)setup_arg[2];
+
+	  if(start < 0 || end > (REMAPPED_FB_LEN-1) || start > end){
+	    // error ... don't skip.
+	    start_skip_save_image_no = (-1);
+	    end_skip_save_image_no = (-1);
+	    return -EINVAL;
+	  }
+
+	  __PRINTK("[w100fb] start=%x, end=%x\n",start,end);
+
+	  if(start != 0 || end != 0){
+	    start = start/IMG_CACHE_MALLOC_SIZE + 1;
+	    end = end/IMG_CACHE_MALLOC_SIZE - 1;
+
+	    __PRINTK("[w100fb] start_no=%x, end_no=%x\n",start,end);
+
+	    if(start <= end){
+	      // do skip.
+	      start_skip_save_image_no = start;
+	      end_skip_save_image_no = end;
+	      return 0;
+	    }
+	  }
+	  // don't skip.
+	  start_skip_save_image_no = (-1);
+	  end_skip_save_image_no = (-1);
+	  return 0;
+	}
+#endif //_IMAGE_CACHE_SUPPORT
+      default:
+	break;
+      }
+    }
+    return -EINVAL;
+    break;
+#endif
+
+  default:
+    return -EINVAL;
+  }
+
+  return 0;
+}
+
+void w100fb_init_from_hwtab(int mode, int fd, char *section, char *item, u32 val)
+{
+  u32 temp32;
+  disp_db_buf_cntl_wr_u disp_db_buf_wr_cntl;
+
+  if (mode == W100INIT_ALL)
+    printk("loading entire hwtab...\n");
+
+  // Prevent display updates
+  disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e; 
+  disp_db_buf_wr_cntl.f.update_db_buf = 0;
+  disp_db_buf_wr_cntl.f.en_db_buf = 0;
+  writel((u32)(disp_db_buf_wr_cntl.val), remapped_regs+mmDISP_DB_BUF_CNTL);
+
+  // Set up the display (NEC 240x320x16)
+
+  // Clock and power management setup
+  if (!strcmp(item, "ClkPinCntl") || mode == W100INIT_ALL)
+  {
+    printk("changing ClkPinCtrl: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x000401BF);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCLK_PIN_CNTL);
+  }
+
+  if (!strcmp(item, "PllRefFBDiv") || mode == W100INIT_ALL)
+  {
+    printk("changing PllRefFBDiv: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x50500D04);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmPLL_REF_FB_DIV);
+  }
+
+  if (!strcmp(item, "PllCntl") || mode == W100INIT_ALL)
+  {
+    printk("changing PllCntl: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x4B000200);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmPLL_CNTL);
+  }
+
+  if (!strcmp(item, "SClkCntl") || mode == W100INIT_ALL)
+  {
+    printk("changing SClkCntl: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000B11);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmSCLK_CNTL);
+  }
+
+  if (!strcmp(item, "PClkCntl") || mode == W100INIT_ALL)
+  {
+    printk("changing PClkCntl: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00008041);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmPCLK_CNTL);
+  }
+
+  if (!strcmp(item, "ClkTestCntl") || mode == W100INIT_ALL)
+  {
+    printk("changing ClkTestCntl: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000001);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCLK_TEST_CNTL);
+  }
+
+  if (!strcmp(item, "PwrMgtCntl") || mode == W100INIT_ALL)
+  {
+    printk("changing PwrMgtCntl: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0xFFFF11C5);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmPWRMGT_CNTL);
+  }
+
+  // LCD setup
+  if (!strcmp(item, "LcdFormat") || mode == W100INIT_ALL)
+  {
+    printk("changing LcdFormat: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00008003);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmLCD_FORMAT);
+  }
+
+  if (!strcmp(item, "GraphicCtrl") || mode == W100INIT_ALL)
+  {
+    printk("changing GraphicCtrl: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00d41c06);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGRAPHIC_CTRL);
+  }
+
+  if (!strcmp(item, "GraphicOffset") || mode == W100INIT_ALL)
+  {
+    printk("changing GraphicOffset: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00100000);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGRAPHIC_OFFSET);
+  }
+
+  if (!strcmp(item, "GraphicPitch") || mode == W100INIT_ALL)
+  {
+    printk("changing GraphicPitch: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x000001e0);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGRAPHIC_PITCH);
+  }
+
+  if (!strcmp(item, "CrtcTotal") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcTotal: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x01510117);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_TOTAL); 
+  }
+
+  if (!strcmp(item, "ActiveHDisp") || mode == W100INIT_ALL)
+  {
+    printk("changing ActiveHDisp: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x01040014);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmACTIVE_H_DISP);
+  }
+
+  if (!strcmp(item, "ActiveVDisp") || mode == W100INIT_ALL)
+  {
+    printk("changing ActiveVDisp: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x01490009);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmACTIVE_V_DISP);
+  }
+
+  if (!strcmp(item, "GraphicHDisp") || mode == W100INIT_ALL)
+  {
+    printk("changing GraphicHDisp: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x01040014);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGRAPHIC_H_DISP);
+  }
+
+  if (!strcmp(item, "GraphicVDisp") || mode == W100INIT_ALL)
+  {
+    printk("changing GraphicVDisp: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x01490009);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGRAPHIC_V_DISP);
+  }
+
+  if (!strcmp(item, "CrtcSS") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcSS: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x80140013);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_SS);
+  }
+
+  if (!strcmp(item, "CrtcLS") || mode == W100INIT_ALL)
+  {
+    printk("chaning CrtsLS: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x800f000a);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_LS);
+  }
+
+  if (!strcmp(item, "CrtcGS") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcGS: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x80050005);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_GS);
+  }
+
+  if (!strcmp(item, "CrtcVPosGS") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcVPosGS: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x000a0009);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_VPOS_GS);
+  }
+
+  if (!strcmp(item, "CrtcGClk") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcGClk: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x8015010f);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_GCLK);
+  }
+
+  if (!strcmp(item, "CrtcGOE") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcGOE: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x80100110);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_GOE);
+  }
+
+  if (!strcmp(item, "CrtcRev") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcRev: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00400008);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_REV);
+  }
+
+  if (!strcmp(item, "CrtcDClk") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcDClk: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x2906000a);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_DCLK);
+  }
+
+  if (!strcmp(item, "CrtcDefaultCount") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcDefaultCount: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000000);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_DEFAULT_COUNT);
+  }
+
+  if (!strcmp(item, "CrtcFrame") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcFrame: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000000);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_FRAME);
+  }
+
+  if (!strcmp(item, "CrtcFrameVPos") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcFrameVPos: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000000);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_FRAME_VPOS);
+  }
+
+  if (!strcmp(item, "LcddCntl2") || mode == W100INIT_ALL)
+  {
+    printk("changing LcddCntl2: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x0003ffff);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmLCDD_CNTL2);
+  }
+
+  if (!strcmp(item, "LcdBackGroundColor") || mode == W100INIT_ALL)
+  {
+    printk("changing LcdBackGroundColor: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x0000ff00);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmLCD_BACKGROUND_COLOR); 
+  }
+
+  if (!strcmp(item, "GpioCntl1") || mode == W100INIT_ALL)
+  {
+    printk("changing GpioCntl1: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000000);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGPIO_CNTL1);
+  }
+
+  if (!strcmp(item, "GenLcdCntl3") || mode == W100INIT_ALL)
+  {
+    printk("changing GenLcdCntl3: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x000102aa);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGENLCD_CNTL3);
+  }
+
+  if (!strcmp(item, "GpioCntl2") || mode == W100INIT_ALL)
+  {
+    printk("changing GpioCntl2: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x03c000ff);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGPIO_CNTL2);
+  }
+
+  if (!strcmp(item, "LcddCntl1") || mode == W100INIT_ALL)
+  {
+    printk("changing LcddCntl1: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000000);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmLCDD_CNTL1);
+  }
+
+  if (!strcmp(item, "GenLcdCntl1") || mode == W100INIT_ALL)
+  {
+    printk("changing GenLcdCntl1: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00fff003);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGENLCD_CNTL1);
+  }
+
+  if (!strcmp(item, "GenLcdCntl2") || mode == W100INIT_ALL)
+  {
+    printk("changing GenLcdCntl2: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x00000003);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmGENLCD_CNTL2);
+  }
+
+  if (!strcmp(item, "CrtcPS1Active") || mode == W100INIT_ALL)
+  {
+    printk("changing CrtcPS1Active: ");
+    if (mode == W100INIT_ITEM_WITH_VAL)
+    {
+      temp32 = val;
+      printk("supplied value is %x (%d)\n", val, val);
+    }
+    else
+    {
+      config_get_dword(fd, section, item, &temp32, 0x41060010);
+      printk("config_get_dword got %x (%d)\n", temp32, temp32);
+    }
+    writel(temp32, remapped_regs+mmCRTC_PS1_ACTIVE);
+  }
+
+  // Re-enable display updates
+  disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e;
+  disp_db_buf_wr_cntl.f.update_db_buf = 1;
+  disp_db_buf_wr_cntl.f.en_db_buf = 1;
+  writel((u32)(disp_db_buf_wr_cntl.val), remapped_regs+mmDISP_DB_BUF_CNTL);
+} 
+
+//
+// The code here supports the use of hardware tables
+// to control the configuration of the driver. The
+// open code attempts to open a file called atihwtbl.conf
+// in /etc. If this file does not exist, calls to config_get_dword
+// will return the default value provided to the call. See frame
+// buffer documentation for a detailed description of hardware
+// tables and how to use them.
+//
+
+//
+// Open the configuration file for read
+// 
+int config_open(const char *config_filename)
+{
+  int fd;
+  mm_segment_t old_fs = get_fs ();
+
+  // Try opening the file name passed to us
+  set_fs(KERNEL_DS);
+  fd = sys_open(config_filename, O_RDONLY, 0);
+  set_fs(old_fs);
+
+  return fd;
+}
+
+//
+// Close the configuration file
+//
+int config_close(int config_fd)
+{
+  // If we have a good fd, let sys_close return it's value, otherwise return -1
+  if (config_fd >= 0)
+    return sys_close(config_fd);
+  else
+  {
+    errno = EBADF;
+    return -1;
+  }
+
+  return 0;
+}
+
+//
+// Get a dword from the configuration file. Find the item specified in id
+// in the group specified by section. Return 0 on success, -1 on failure.
+// On failure, the value returned in val is unspecified.
+//
+int config_get_dword(int config_fd, const char *section, const char *id, u32 *val, u32 defval)
+{
+  int x;
+  char *local_sec, *local_id, *local_val;
+  char line_buffer[256];
+  long retval;
+  mm_segment_t oldfs;
+
+  // Sanity check
+  if (config_fd < 0 || section == NULL || id == NULL || val == NULL)
+  {
+    errno = EINVAL;
+    *val = defval;
+    return -1;
+  }
+
+  local_sec = kmalloc(strlen(section)+3, GFP_KERNEL);
+  strcpy(local_sec, "[");
+  strcat(local_sec, section);
+  strcat(local_sec, "]");
+
+  local_id = kmalloc(strlen(id)+3, GFP_KERNEL);
+  strcpy(local_id, "\"");
+  strcat(local_id, id);
+  strcat(local_id, "\"");
+
+  // First, find the requested section
+  while (1)
+  {
+    memset(line_buffer, '\0', 256);
+    oldfs = get_fs();
+    set_fs(KERNEL_DS);
+    for (x = 0; x < 256; x++)
+    {
+      if (!sys_read(config_fd, &line_buffer[x], 1))
+	goto done;
+      if (line_buffer[x] == '\n' || line_buffer[x] == '\r')
+	break;
+    }
+    set_fs(oldfs);
+
+    if (!strncmp(line_buffer, "//", 2))
+      continue;
+
+    if (!strncmp(line_buffer, local_sec, strlen(local_sec)))
+    {
+      // Now find the id and extract the value
+      while (1)
+      {
+	memset(line_buffer, '\0', 256);
+	oldfs = get_fs();
+	set_fs(KERNEL_DS);
+	for (x = 0; x < 256; x++)
+	{
+	  if (!sys_read(config_fd, &line_buffer[x], 1))
+	    goto done;
+	  if (line_buffer[x] == '\n' || line_buffer[x] == '\r')
+	    break;
+	}
+	set_fs(oldfs);
+
+	// If the new line starts with a '[', it's probably a
+	// section header so skip it
+	if (line_buffer[0] == '[')
+	  continue;
+	if (!strncmp(line_buffer, local_id, strlen(local_id)))
+	{
+	  // We found the id, now extract the value
+	  local_val = strpbrk(line_buffer, ":");
+	  local_val++;
+	  // If the value starts with an 0x it's hex otherwise, assume dec
+	  if (!strncmp(local_val, "0x", 2))
+	    retval = my_strtol(local_val, NULL, 16);
+	  else
+	    retval = my_strtol(local_val, NULL, 10);
+	  *val = retval;
+	  // free the local buffers
+	  kfree(local_id);
+	  kfree(local_sec);
+	  return 0;
+	}
+      }  
+    }
+  }
+ done:
+  // Didn't find it, free local buffers and indicate the error
+  kfree(local_id);
+  kfree(local_sec);
+  errno = EINVAL;
+  *val = defval;
+  return -1;
+}
+
+static char cvtIn[] = {
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9,		  /* '0' - '9' */
+  100, 100, 100, 100, 100, 100, 100,	  /* punctuation */
+  10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'A' - 'Z' */
+  20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+  30, 31, 32, 33, 34, 35,
+  100, 100, 100, 100, 100, 100,		  /* punctuation */
+  10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'a' - 'z' */
+  20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+  30, 31, 32, 33, 34, 35};
+
+int isspace(int x)
+{
+  return x == ' ' || (x >= '\b' && x <= '\r');
+}
+
+unsigned long my_strtoul(const char *string, char **endPtr, int base)
+{
+  register const char *p;
+  register unsigned long int result = 0;
+  register unsigned digit;
+  int anyDigits = 0;
+  int negative=0;
+  int overflow=0;
+
+  /*
+   * Skip any leading blanks.
+   */
+
+  p = string;
+  while (isspace((unsigned char)(*p)))
+  {
+    p += 1;
+  }
+  if (*p == '-')
+  {
+    negative = 1;
+    p += 1;
+  }
+  else
+  {
+    if (*p == '+')
+    {
+      p += 1;
+    }
+  }
+
+  /*
+   * If no base was provided, pick one from the leading characters
+   * of the string.
+  */
+  if (base == 0)
+  {
+    if (*p == '0')
+    {
+      p += 1;
+      if ((*p == 'x') || (*p == 'X'))
+      {
+	p += 1;
+	base = 16;
+      }
+      else
+      {
+	/*
+	 * Must set anyDigits here, otherwise "0" produces a
+	 * "no digits" error.
+	 */
+
+	anyDigits = 1;
+	base = 8;
+      }
+    }
+    else
+      base = 10;
+  } 
+  else if (base == 16)
+  {
+    /*
+     * Skip a leading "0x" from hex numbers.
+     */
+
+    if ((p[0] == '0') && ((p[1] == 'x') || (p[1] == 'X')))
+    {
+      p += 2;
+    }
+  }
+
+  /*
+   * Sorry this code is so messy, but speed seems important.  Do
+   * different things for base 8, 10, 16, and other.
+   */
+
+  if (base == 8)
+  {
+    unsigned long maxres = ULONG_MAX >> 3;
+    for ( ; ; p += 1)
+    {
+      digit = *p - '0';
+      if (digit > 7)
+      {
+	break;
+      }
+      if (result > maxres)
+      { 
+	overflow = 1;
+      }
+      result = (result << 3);
+      if (digit > (ULONG_MAX - result))
+      {
+	overflow = 1; 
+      }
+      result += digit;
+      anyDigits = 1;
+    }
+  }
+  else if (base == 10) 
+  {
+    unsigned long maxres = ULONG_MAX / 10;
+    for ( ; ; p += 1)
+    {
+      digit = *p - '0';
+      if (digit > 9)
+      {
+	break;
+      }
+      if (result > maxres)
+      {
+	overflow = 1;
+      }
+      result *= 10;
+      if (digit > (ULONG_MAX - result))
+      {
+	overflow = 1;
+      }
+      result += digit;
+      anyDigits = 1;
+    }
+  }
+  else if (base == 16)
+  {
+    unsigned long maxres = ULONG_MAX >> 4;
+    for ( ; ; p += 1)
+    {
+      digit = *p - '0';
+      if (digit > ('z' - '0'))
+      {
+	break;
+      }
+      digit = cvtIn[digit];
+      if (digit > 15)
+      {
+	break;
+      }
+      if (result > maxres)
+      { 
+	overflow = 1; 
+      }
+      result = (result << 4);
+      if (digit > (ULONG_MAX - result)) 
+      {
+	overflow = 1; 
+      }
+      result += digit;
+      anyDigits = 1;
+    }
+  }
+  else if ( base >= 2 && base <= 36 )
+  {
+    unsigned long maxres = ULONG_MAX / base;
+    for ( ; ; p += 1)
+    {
+      digit = *p - '0';
+      if (digit > ('z' - '0'))
+      {
+	break;
+      }
+      digit = cvtIn[digit];
+      if (digit >= ( (unsigned) base ))
+      {
+	break;
+      }
+      if (result > maxres)
+      { 
+	overflow = 1;
+      }
+      result *= base;
+      if (digit > (ULONG_MAX - result))
+      { 
+	overflow = 1;
+      }
+      result += digit;
+      anyDigits = 1;
+    }
+  }
+
+  /*
+   * See if there were any digits at all.
+   */
+
+  if (!anyDigits)
+  {
+    p = string;
+  }
+
+  if (endPtr != 0)
+  {
+    /* unsafe, but required by the strtoul prototype */
+    *endPtr = (char *) p;
+  }
+
+  if (overflow)
+  {
+    errno = ERANGE;
+    return ULONG_MAX;
+  } 
+  if (negative)
+  {
+    return -result;
+  }
+  return result;
+}
+
+long my_strtol(const char *string, char **endPtr, int base)
+{
+  register const char *p;
+  long result;
+
+  /*
+   * Skip any leading blanks.
+   */
+
+  p = string;
+  while (isspace((unsigned char)(*p)))
+  {
+    p += 1;
+  }
+
+  /*
+   * Check for a sign.
+   */
+
+  if (*p == '-')
+  {
+    p += 1;
+    result = -(my_strtoul(p, endPtr, base));
+  }
+  else
+  {
+    if (*p == '+')
+    {
+      p += 1;
+    }
+    result = my_strtoul(p, endPtr, base);
+  }
+  if ((result == 0) && (endPtr != 0) && (*endPtr == p))
+  {
+    *endPtr = (char *) string;
+  }
+  return result;
+}
+
+
+//
+// Constants
+//
+
+#define SUCCESS 1
+#define ERROR   0
+
+
+//
+// Types
+//
+
+typedef struct pll_parm
+{
+    u16 Freq;       // desired Fout for PLL
+    u8  M;
+    u8  N_int;
+    u8  N_fac;
+    u8  tfgoal;
+    u8  lock_time;
+} pll_parm_t;
+
+typedef struct
+{
+    clk_pin_cntl_u    clk_pin_cntl;
+    pll_ref_fb_div_u  pll_ref_fb_div;
+    pll_cntl_u        pll_cntl;
+    sclk_cntl_u       sclk_cntl;
+    pclk_cntl_u       pclk_cntl;
+    clk_test_cntl_u   clk_test_cntl;
+    pwrmgt_cntl_u     pwrmgt_cntl;
+    u32               Freq;           // Fout for PLL calibration
+    u8                tf100;          // for pll calibration
+    u8                tf80;           // for pll calibration
+    u8                tf20;           // for pll calibration
+    u8                M;              // for pll calibration
+    u8                N_int;          // for pll calibration
+    u8                N_fac;          // for pll calibration
+    u8                lock_time;      // for pll calibration
+    u8                tfgoal;         // for pll calibration
+    u8                AutoMode;       // hardware auto switch?
+    u8                PWMMode;        // 0 fast, 1 normal/slow
+    u16               FastSclk;       // fast clk freq
+    u16               NormSclk;       // slow clk freq
+} power_state_t;
+
+
+//
+// Global state variables
+//
+
+static power_state_t gPowerState;
+
+#ifdef USE_XTAL_12_5
+// This table is specific for 12.5MHz ref crystal.
+static pll_parm_t gPLLTable[] =
+{
+    //Freq     M   N_int    N_fac  tfgoal  lock_time
+    { 50,      0,   1,       0,     0xE0,        56}, //  50.00 MHz
+    { 75,      0,   5,       0,     0xDE,	 37}, //  75.00 MHz
+    {100,      0,   7,       0,     0xE0,        28}, // 100.00 MHz 
+    {  0,      0,   0,       0,        0,         0}  // Terminator
+};
+#else
+// This table is specific for the 14.3MHz ref crystal found on a W100 board.
+static pll_parm_t gPLLTable[] =
+{
+    //Freq     M   N_int    N_fac  tfgoal  lock_time
+    { 50,      1,   6,       0,     0xE0,	 64}, //  50.05 MHz
+    { 75,      0,   4,       3,     0xE0,	 43}, //  75.08 MHz
+    {100,      0,   6,       0,     0xE0,        32}, // 100.10 MHz
+    {  0,      0,   0,       0,        0,         0}  // Terminator
+};
+#endif
+
+
+// making delay by reading our chipid;
+// also known as CORE_DELAY_US.
+static void w100fb_Delay(u32 Count)
+{
+    udelay(Count);
+} // w100fb_Delay
+
+
+static u8 w100fb_GetPLLTestCount( u8 testclk_sel)
+{
+  w100fb_Delay(5);		//delay 5 us
+
+  gPowerState.clk_test_cntl.f.start_check_freq = 0x0;
+  gPowerState.clk_test_cntl.f.testclk_sel      = testclk_sel;
+  gPowerState.clk_test_cntl.f.tstcount_rst     = 0x1; //reset test count
+  writel((u32)(gPowerState.clk_test_cntl.val), remapped_regs+mmCLK_TEST_CNTL);
+  gPowerState.clk_test_cntl.f.tstcount_rst     = 0x0;
+  writel((u32)(gPowerState.clk_test_cntl.val), remapped_regs+mmCLK_TEST_CNTL);
+
+  gPowerState.clk_test_cntl.f.start_check_freq = 0x1;
+  writel((u32)(gPowerState.clk_test_cntl.val), remapped_regs+mmCLK_TEST_CNTL);
+
+  w100fb_Delay(20);		//delay 20 us
+
+  gPowerState.clk_test_cntl.val = readl(remapped_regs+mmCLK_TEST_CNTL);
+  gPowerState.clk_test_cntl.f.start_check_freq = 0x0;
+  writel((u32)(gPowerState.clk_test_cntl.val), remapped_regs+mmCLK_TEST_CNTL);
+
+  return(gPowerState.clk_test_cntl.f.test_count);
+} // w100fb_GetPLLTestCount
+
+
+static s8 w100fb_AdjustPLL(void)
+{
+  do
+  {
+    // Wai Ming 80 percent of VDD 1.3V gives 1.04V, minimum operating voltage is 1.08V
+    // therefore, commented out the following lines
+    // tf80 meant tf100
+    // set VCO input = 0.8 * VDD
+    gPowerState.pll_cntl.f.pll_dactal = 0xd;
+    writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+    gPowerState.tf80 = w100fb_GetPLLTestCount( 0x1); // PLLCLK
+    if (gPowerState.tf80 >= (gPowerState.tfgoal))
+    {
+      // set VCO input = 0.2 * VDD
+      gPowerState.pll_cntl.f.pll_dactal = 0x7;
+      writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+      gPowerState.tf20 = w100fb_GetPLLTestCount( 0x1); // PLLCLK
+      if (gPowerState.tf20 <= (gPowerState.tfgoal))
+        return( SUCCESS );
+
+      if ((gPowerState.pll_cntl.f.pll_vcofr   == 0x0) &&
+         ((gPowerState.pll_cntl.f.pll_pvg     == 0x7) ||
+          (gPowerState.pll_cntl.f.pll_ioffset == 0x0)))
+      {
+        // slow VCO config
+        gPowerState.pll_cntl.f.pll_vcofr   = 0x1;
+        gPowerState.pll_cntl.f.pll_pvg     = 0x0;
+        gPowerState.pll_cntl.f.pll_ioffset = 0x0;
+        writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+        continue;
+      }
+    }
+    if ((gPowerState.pll_cntl.f.pll_ioffset) < 0x3)
+    {
+      gPowerState.pll_cntl.f.pll_ioffset += 0x1;
+      writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+      continue;
+    }
+    if ((gPowerState.pll_cntl.f.pll_pvg) < 0x7)
+    {
+      gPowerState.pll_cntl.f.pll_ioffset = 0x0;
+      gPowerState.pll_cntl.f.pll_pvg    += 0x1;
+      writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+      continue;
+    }
+    return( ERROR);
+  } while (1);
+} // w100fb_AdjustPLL
+
+
+//********************************************************************
+// w100fb_PLL_Calibration
+//                freq = target frequency of the PLL
+//                (note: crystal = 14.3MHz)
+//********************************************************************
+static s8 w100fb_PLL_Calibration( u32 freq)
+{
+    s8 status = SUCCESS;
+
+    // initial setting
+    gPowerState.pll_cntl.f.pll_pwdn     = 0x0; // power down
+    gPowerState.pll_cntl.f.pll_reset    = 0x0; // not reset
+    gPowerState.pll_cntl.f.pll_tcpoff   = 0x1; // Hi-Z
+    gPowerState.pll_cntl.f.pll_pvg      = 0x0; // VCO gain = 0
+    gPowerState.pll_cntl.f.pll_vcofr    = 0x0; // VCO frequency range control = off
+    gPowerState.pll_cntl.f.pll_ioffset  = 0x0; // current offset inside VCO = 0
+    gPowerState.pll_cntl.f.pll_ring_off = 0x0; //
+    writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+    // check for (tf80 >= tfgoal) && (tf20 =< tfgoal)
+    if ((gPowerState.tf80 < gPowerState.tfgoal) || (gPowerState.tf20 > gPowerState.tfgoal))
+    {
+        if (w100fb_AdjustPLL() == ERROR)
+        {
+            status = ERROR;
+        }
+    }
+
+    // PLL Reset And Lock
+
+    //set VCO input = 0.5 * VDD
+    gPowerState.pll_cntl.f.pll_dactal = 0xa;
+    writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+    // reset time
+    w100fb_Delay(1);                // delay 1 us
+
+    // enable charge pump
+    gPowerState.pll_cntl.f.pll_tcpoff = 0x0; // normal
+    writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+    // set VCO input = Hi-Z
+    // disable DAC
+    gPowerState.pll_cntl.f.pll_dactal = 0x0;
+    writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+    // lock time
+    w100fb_Delay(400);                // delay 400 us
+
+    // PLL locked
+
+    gPowerState.sclk_cntl.f.sclk_src_sel = 0x1; // PLL clock
+    writel((u32)(gPowerState.sclk_cntl.val), remapped_regs+mmSCLK_CNTL);
+
+    gPowerState.tf100 = w100fb_GetPLLTestCount( 0x1); // PLLCLK
+
+    return( status );
+} // w100fb_PLL_Calibration
+
+
+static s8 w100fb_SetPllClk(void)
+{
+    u8 status;
+
+    if (gPowerState.AutoMode == 1) // auto mode
+    {
+        gPowerState.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0; // disable fast to normal
+        gPowerState.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0; // disable normal to fast
+        writel((u32)(gPowerState.pwrmgt_cntl.val), remapped_regs+mmPWRMGT_CNTL);
+    }
+
+    gPowerState.sclk_cntl.f.sclk_src_sel    = 0x0; // crystal clock
+    writel((u32)(gPowerState.sclk_cntl.val), remapped_regs+mmSCLK_CNTL);
+
+    gPowerState.pll_ref_fb_div.f.pll_ref_div     = gPowerState.M;
+    gPowerState.pll_ref_fb_div.f.pll_fb_div_int  = gPowerState.N_int;
+    gPowerState.pll_ref_fb_div.f.pll_fb_div_frac = gPowerState.N_fac;
+    gPowerState.pll_ref_fb_div.f.pll_lock_time   = gPowerState.lock_time;
+    writel((u32)(gPowerState.pll_ref_fb_div.val), remapped_regs+mmPLL_REF_FB_DIV);
+
+    gPowerState.pwrmgt_cntl.f.pwm_mode_req = 0;
+    writel((u32)(gPowerState.pwrmgt_cntl.val), remapped_regs+mmPWRMGT_CNTL);
+
+    // w100fb_Delay(400);  //delay 400 us
+
+    status = w100fb_PLL_Calibration( gPowerState.Freq);
+
+    // gPowerState.sclk_cntl.f.sclk_src_sel    = 0x1; //PLL clock
+    // writel((u32)(gPowerState.sclk_cntl.val), remapped_regs+mmSCLK_CNTL);
+
+    if (gPowerState.AutoMode == 1) // auto mode
+    {
+        gPowerState.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x1; // reenable fast to normal
+        gPowerState.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x1; // reenable normal to fast 
+        writel((u32)(gPowerState.pwrmgt_cntl.val), remapped_regs+mmPWRMGT_CNTL);
+    }
+    return( status );
+} // w100fb_SetPllClk
+
+
+// assume reference crystal clk is 12.5MHz,
+// and that doubling is not enabled.
+//
+// Freq = 12 == 12.5MHz.
+static u16 w100fb_SetSlowSysClk(u16 Freq)
+{
+  if (gPowerState.NormSclk == Freq)
+    return(Freq);
+
+  if (gPowerState.AutoMode == 1) //auto mode
+    return(0);
+
+  if (Freq == 12)
+  {
+      gPowerState.NormSclk = Freq;
+      gPowerState.sclk_cntl.f.sclk_post_div_slow    = 0x0; // Pslow = 1
+      gPowerState.sclk_cntl.f.sclk_src_sel          = 0x0; // crystal src
+
+      writel((u32)(gPowerState.sclk_cntl.val), remapped_regs+mmSCLK_CNTL);
+
+      gPowerState.clk_pin_cntl.f.xtalin_pm_en       = 0x1;
+      writel((u32)(gPowerState.clk_pin_cntl.val), remapped_regs+mmCLK_PIN_CNTL);
+
+      //gPowerState.pll_cntl.f.pll_pm_en               = 0x0;
+      //writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+      gPowerState.pwrmgt_cntl.f.pwm_enable          = 0x1;
+      gPowerState.pwrmgt_cntl.f.pwm_mode_req        = 0x1;
+      writel((u32)(gPowerState.pwrmgt_cntl.val), remapped_regs+mmPWRMGT_CNTL);
+      gPowerState.PWMMode  = 1;	//normal mode
+      return(Freq);
+  }
+  else
+  {
+      return (0);
+  }
+} // w100fb_SetSlowSysClk
+
+
+static u16 w100fb_SetFastSysClk(u16 Freq)
+{
+    u16        PLLFreq;
+    int i;
+
+    while (1)
+    {
+        PLLFreq = (u16)(Freq * (gPowerState.sclk_cntl.f.sclk_post_div_fast + 1));
+        i = 0;
+        do
+        {
+            if (PLLFreq == gPLLTable[i].Freq)
+            {
+                gPowerState.Freq      = gPLLTable[i].Freq * 1000000;
+                gPowerState.M         = gPLLTable[i].M;
+                gPowerState.N_int     = gPLLTable[i].N_int;
+                gPowerState.N_fac     = gPLLTable[i].N_fac;
+                gPowerState.tfgoal    = gPLLTable[i].tfgoal;
+                gPowerState.lock_time = gPLLTable[i].lock_time;
+                gPowerState.tf20      = 0xff;  // set highest
+                gPowerState.tf80      = 0x00;  // set lowest
+
+                w100fb_SetPllClk();
+                gPowerState.PWMMode  = 0;      // fast mode
+                gPowerState.FastSclk = Freq;
+                return(Freq);
+            }
+            i++;
+        } while (gPLLTable[i].Freq);
+
+        if (gPowerState.AutoMode == 1) break;
+
+        if (gPowerState.sclk_cntl.f.sclk_post_div_fast == 0) break;
+
+        gPowerState.sclk_cntl.f.sclk_post_div_fast -= 1;
+        writel((u32)(gPowerState.sclk_cntl.val), remapped_regs+mmSCLK_CNTL);
+    }
+    return(0);
+} // w100fb_SetFastSysClk
+
+
+// Set up an initial state.  Some values/fields set
+// here will be overwritten.
+static void w100fb_PwmSetup(void)
+{
+    gPowerState.clk_pin_cntl.f.osc_en             = 0x1;
+    gPowerState.clk_pin_cntl.f.osc_gain           = 0x1f;
+    gPowerState.clk_pin_cntl.f.dont_use_xtalin    = 0x0;
+    gPowerState.clk_pin_cntl.f.xtalin_pm_en       = 0x0;
+    gPowerState.clk_pin_cntl.f.xtalin_dbl_en      = 0x0; // no freq doubling
+    gPowerState.clk_pin_cntl.f.cg_debug           = 0x0;
+    writel((u32)(gPowerState.clk_pin_cntl.val), remapped_regs+mmCLK_PIN_CNTL);
+
+    gPowerState.sclk_cntl.f.sclk_src_sel          = 0x0; // Crystal Clk
+    gPowerState.sclk_cntl.f.sclk_post_div_fast    = 0x0; // Pfast = 1
+    gPowerState.sclk_cntl.f.sclk_clkon_hys        = 0x3;
+    gPowerState.sclk_cntl.f.sclk_post_div_slow    = 0x0; // Pslow = 1
+    gPowerState.sclk_cntl.f.disp_cg_ok2switch_en  = 0x0;
+    gPowerState.sclk_cntl.f.sclk_force_reg        = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_disp       = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_mc         = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_extmc      = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_cp         = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_e2         = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_e3         = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_idct       = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.sclk_force_bist       = 0x0; // Dynamic
+    gPowerState.sclk_cntl.f.busy_extend_cp        = 0x0;
+    gPowerState.sclk_cntl.f.busy_extend_e2        = 0x0;
+    gPowerState.sclk_cntl.f.busy_extend_e3        = 0x0;
+    gPowerState.sclk_cntl.f.busy_extend_idct      = 0x0;
+    writel((u32)(gPowerState.sclk_cntl.val), remapped_regs+mmSCLK_CNTL);
+
+    gPowerState.pclk_cntl.f.pclk_src_sel          = 0x0; // Crystal Clk
+    gPowerState.pclk_cntl.f.pclk_post_div         = 0x1; // P = 2
+    gPowerState.pclk_cntl.f.pclk_force_disp       = 0x0; // Dynamic
+    writel((u32)(gPowerState.pclk_cntl.val), remapped_regs+mmPCLK_CNTL);
+
+    gPowerState.pll_ref_fb_div.f.pll_ref_div      = 0x0; // M = 1
+    gPowerState.pll_ref_fb_div.f.pll_fb_div_int   = 0x0; // N = 1.0
+    gPowerState.pll_ref_fb_div.f.pll_fb_div_frac  = 0x0;
+    gPowerState.pll_ref_fb_div.f.pll_reset_time   = 0x5;
+    gPowerState.pll_ref_fb_div.f.pll_lock_time    = 0xff;
+    writel((u32)(gPowerState.pll_ref_fb_div.val), remapped_regs+mmPLL_REF_FB_DIV);
+
+    gPowerState.pll_cntl.f.pll_pwdn               = 0x1;
+    gPowerState.pll_cntl.f.pll_reset              = 0x1;
+    gPowerState.pll_cntl.f.pll_pm_en              = 0x0;
+    gPowerState.pll_cntl.f.pll_mode               = 0x0; // uses VCO clock
+    gPowerState.pll_cntl.f.pll_refclk_sel         = 0x0;
+    gPowerState.pll_cntl.f.pll_fbclk_sel          = 0x0;
+    gPowerState.pll_cntl.f.pll_tcpoff             = 0x0;
+    gPowerState.pll_cntl.f.pll_pcp                = 0x4;
+    gPowerState.pll_cntl.f.pll_pvg                = 0x0;
+    gPowerState.pll_cntl.f.pll_vcofr              = 0x0;
+    gPowerState.pll_cntl.f.pll_ioffset            = 0x0;
+    gPowerState.pll_cntl.f.pll_pecc_mode          = 0x0;
+    gPowerState.pll_cntl.f.pll_pecc_scon          = 0x0;
+    gPowerState.pll_cntl.f.pll_dactal             = 0x0; // Hi-Z
+    gPowerState.pll_cntl.f.pll_cp_clip            = 0x3;
+    gPowerState.pll_cntl.f.pll_conf               = 0x2;
+    gPowerState.pll_cntl.f.pll_mbctrl             = 0x2;
+    gPowerState.pll_cntl.f.pll_ring_off           = 0x0;
+    writel((u32)(gPowerState.pll_cntl.val), remapped_regs+mmPLL_CNTL);
+
+    gPowerState.clk_test_cntl.f.testclk_sel       = 0x1; // PLLCLK (for testing)
+    gPowerState.clk_test_cntl.f.start_check_freq  = 0x0;
+    gPowerState.clk_test_cntl.f.tstcount_rst      = 0x0;
+    writel((u32)(gPowerState.clk_test_cntl.val), remapped_regs+mmCLK_TEST_CNTL);
+
+    gPowerState.pwrmgt_cntl.f.pwm_enable          = 0x0;
+    gPowerState.pwrmgt_cntl.f.pwm_mode_req        = 0x1; // normal mode (0, 1, 3)
+    gPowerState.pwrmgt_cntl.f.pwm_wakeup_cond     = 0x0;
+    gPowerState.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0;
+    gPowerState.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0;
+    gPowerState.pwrmgt_cntl.f.pwm_fast_noml_cond  = 0x1; // PM4,ENG
+    gPowerState.pwrmgt_cntl.f.pwm_noml_fast_cond  = 0x1; // PM4,ENG
+    gPowerState.pwrmgt_cntl.f.pwm_idle_timer      = 0xFF;
+    gPowerState.pwrmgt_cntl.f.pwm_busy_timer      = 0xFF;
+    writel((u32)(gPowerState.pwrmgt_cntl.val), remapped_regs+mmPWRMGT_CNTL);
+
+    gPowerState.AutoMode                          = 0;        // manual mode
+    gPowerState.PWMMode                           = 1;        // normal mode (0, 1, 2)
+    gPowerState.Freq                              = 50000000; // 50 MHz
+    gPowerState.M                                 = 3;        // M = 4
+    gPowerState.N_int                             = 6;        // N = 7.0
+    gPowerState.N_fac                             = 0;        //
+    gPowerState.tfgoal                            = 0xE0;
+    gPowerState.lock_time                         = 56;
+    gPowerState.tf20                              = 0xff;     // set highest
+    gPowerState.tf80                              = 0x00;     // set lowest
+    gPowerState.tf100                             = 0x00;     // set lowest
+    gPowerState.FastSclk                          = 50;       // 50.0 MHz
+    gPowerState.NormSclk                          = 12;       // 12.5 MHz
+} // w100fb_PwmSetup
+
+
+static void w100fb_init_sharp_lcd(u32 mode)
+{
+    u32 temp32;
+    disp_db_buf_cntl_wr_u disp_db_buf_wr_cntl;
+
+    // Prevent display updates
+    disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e; 
+    disp_db_buf_wr_cntl.f.update_db_buf = 0;
+    disp_db_buf_wr_cntl.f.en_db_buf = 0;
+    writel((u32)(disp_db_buf_wr_cntl.val), remapped_regs+mmDISP_DB_BUF_CNTL);
+
+    switch (mode)
+    {
+        case LCD_SHARP_QVGA:
+            w100fb_SetSlowSysClk(12);  // use crystal -- 12.5MHz
+#if 0  	    // not use PLL
+            w100fb_SetFastSysClk(50);  // use PLL     -- 50.0MHz
+#endif
+	    writel(0x7FFF8000, remapped_regs+mmMC_EXT_MEM_LOCATION);
+	    writel(0x85FF8000, remapped_regs+mmMC_FB_LOCATION);
+            writel(0x00000003, remapped_regs+mmLCD_FORMAT);
+            writel(0x00CF1C06, remapped_regs+mmGRAPHIC_CTRL);
+            writel(0x01410145, remapped_regs+mmCRTC_TOTAL); 
+            writel(0x01170027, remapped_regs+mmACTIVE_H_DISP);
+            writel(0x01410001, remapped_regs+mmACTIVE_V_DISP);
+            writel(0x01170027, remapped_regs+mmGRAPHIC_H_DISP);
+            writel(0x01410001, remapped_regs+mmGRAPHIC_V_DISP);
+            writel(0x81170027, remapped_regs+mmCRTC_SS);
+            writel(0xA0140000, remapped_regs+mmCRTC_LS);
+            writel(0x00400008, remapped_regs+mmCRTC_REV);
+	    writel(0xA0000000, remapped_regs+mmCRTC_DCLK);
+	    writel(0xC0140014, remapped_regs+mmCRTC_GS);
+            writel(0x00010141, remapped_regs+mmCRTC_VPOS_GS);
+            writel(0x8015010F, remapped_regs+mmCRTC_GCLK);
+            writel(0x80100110, remapped_regs+mmCRTC_GOE);
+            writel(0x00000000, remapped_regs+mmCRTC_FRAME);
+            writel(0x00000000, remapped_regs+mmCRTC_FRAME_VPOS);
+            writel(0x01CC0000, remapped_regs+mmLCDD_CNTL1);
+            writel(0x0003FFFF, remapped_regs+mmLCDD_CNTL2);
+            writel(0x00FFFF0D, remapped_regs+mmGENLCD_CNTL1);
+	    writel(0x003F3003, remapped_regs+mmGENLCD_CNTL2);
+            writel(0x00000000, remapped_regs+mmCRTC_DEFAULT_COUNT);
+            writel(0x0000FF00, remapped_regs+mmLCD_BACKGROUND_COLOR); 
+            // hmm ...
+            writel(0x000102aa, remapped_regs+mmGENLCD_CNTL3);
+            // hmm ...
+	    writel(0x00800000, remapped_regs+mmGRAPHIC_OFFSET);
+            writel(0x000001e0, remapped_regs+mmGRAPHIC_PITCH);
+            // hmm ...
+            writel(0x000000bf, remapped_regs+mmGPIO_DATA);
+	    writel(0x03c0feff, remapped_regs+mmGPIO_CNTL2);
+            writel(0x00000000, remapped_regs+mmGPIO_CNTL1);
+            writel(0x41060010, remapped_regs+mmCRTC_PS1_ACTIVE);
+            break;
+        case LCD_SHARP_VGA:
+            w100fb_SetSlowSysClk(12);  // use crystal -- 12.5MHz
+            w100fb_SetFastSysClk(75);  // use PLL     -- 75.0MHz
+            gPowerState.pclk_cntl.f.pclk_src_sel  = 0x1;
+            gPowerState.pclk_cntl.f.pclk_post_div = 0x2;
+            writel((u32)(gPowerState.pclk_cntl.val), remapped_regs+mmPCLK_CNTL);
+            writel(0x15FF1000, remapped_regs+mmMC_FB_LOCATION);
+	    writel(0x9FFF8000, remapped_regs+mmMC_EXT_MEM_LOCATION);
+            writel(0x00000003, remapped_regs+mmLCD_FORMAT);
+	    writel(0x00DE1D66, remapped_regs+mmGRAPHIC_CTRL);
+
+            writel(0x0283028B, remapped_regs+mmCRTC_TOTAL); 
+            writel(0x02360056, remapped_regs+mmACTIVE_H_DISP);
+            writel(0x02830003, remapped_regs+mmACTIVE_V_DISP);
+            writel(0x02360056, remapped_regs+mmGRAPHIC_H_DISP);
+            writel(0x02830003, remapped_regs+mmGRAPHIC_V_DISP);
+            writel(0x82360056, remapped_regs+mmCRTC_SS);
+            writel(0xA0280000, remapped_regs+mmCRTC_LS);
+            writel(0x00400008, remapped_regs+mmCRTC_REV);
+	    writel(0xA0000000, remapped_regs+mmCRTC_DCLK);
+	    writel(0x80280028, remapped_regs+mmCRTC_GS);
+            writel(0x02830002, remapped_regs+mmCRTC_VPOS_GS);
+            writel(0x8015010F, remapped_regs+mmCRTC_GCLK);
+            writel(0x80100110, remapped_regs+mmCRTC_GOE);
+            writel(0x00000000, remapped_regs+mmCRTC_FRAME);
+            writel(0x00000000, remapped_regs+mmCRTC_FRAME_VPOS);
+            writel(0x01CC0000, remapped_regs+mmLCDD_CNTL1);
+            writel(0x0003FFFF, remapped_regs+mmLCDD_CNTL2);
+            writel(0x00FFFF0D, remapped_regs+mmGENLCD_CNTL1);
+	    writel(0x003F3003, remapped_regs+mmGENLCD_CNTL2);
+            writel(0x00000000, remapped_regs+mmCRTC_DEFAULT_COUNT);
+            writel(0x0000FF00, remapped_regs+mmLCD_BACKGROUND_COLOR); 
+            // hmm ...
+            writel(0x000102aa, remapped_regs+mmGENLCD_CNTL3);
+            // hmm ...
+            writel(0x00800000, remapped_regs+mmGRAPHIC_OFFSET);
+            writel(0x000003C0, remapped_regs+mmGRAPHIC_PITCH);
+            // hmm ...
+            writel(0x000000bf, remapped_regs+mmGPIO_DATA);
+	    writel(0x03c0feff, remapped_regs+mmGPIO_CNTL2);
+            writel(0x00000000, remapped_regs+mmGPIO_CNTL1);
+            writel(0x41060010, remapped_regs+mmCRTC_PS1_ACTIVE);
+            break;
+        default:
+            break;
+    }
+
+    // Hack for overlay in ext memory
+    temp32 = readl(remapped_regs+mmDISP_DEBUG2);
+    temp32 |= 0xc0000000;
+    writel(temp32, remapped_regs+mmDISP_DEBUG2);
+
+    // Re-enable display updates
+    disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e;
+    disp_db_buf_wr_cntl.f.update_db_buf = 1;
+    disp_db_buf_wr_cntl.f.en_db_buf = 1;
+    writel((u32)(disp_db_buf_wr_cntl.val), remapped_regs+mmDISP_DB_BUF_CNTL);
+} // w100fb_init_sharp_lcd
+
+static void w100fb_init_qvga_rotation(u16 deg)
+{
+    // for resolution change and rotation
+    // GRAPHIC_CTRL
+    // GRAPHIC_OFFSET
+    // GRAPHIC_PITCH
+
+    switch(deg){
+    case 0:
+	writel(0x00d41c06, remapped_regs+mmGRAPHIC_CTRL);
+	writel(0x00800000, remapped_regs+mmGRAPHIC_OFFSET);
+	writel(0x000001e0, remapped_regs+mmGRAPHIC_PITCH);
+	break;
+    case 270:
+	writel(0x00d41c16, remapped_regs+mmGRAPHIC_CTRL);
+	//writel(0x0080027e, remapped_regs+mmGRAPHIC_OFFSET);
+	writel(0x0080027c, remapped_regs+mmGRAPHIC_OFFSET);
+	writel(0x00000280, remapped_regs+mmGRAPHIC_PITCH);
+	break;
+    default:
+	// not-support
+	break;
+    }
+}
+
+static void w100fb_suspend(u32 mode)
+{
+    u32 val;
+
+    writel(0x7FFF8000, remapped_regs+mmMC_EXT_MEM_LOCATION);
+    writel(0x00FF0000, remapped_regs+mmMC_PERF_MON_CNTL);
+
+    val = readl(remapped_regs+mmMEM_EXT_TIMING_CNTL);
+    val &= ~(0x00100000); // bit20=0
+    val |= 0xFF000000;    // bit31:24=0xff
+    writel(val, remapped_regs+mmMEM_EXT_TIMING_CNTL);
+
+    val = readl(remapped_regs+mmMEM_EXT_CNTL);
+    val &= ~(0x00040000); // bit18=0
+    val |= 0x00080000;    // bit19=1
+    writel(val, remapped_regs+mmMEM_EXT_CNTL);
+
+    udelay(1); // wait 1us
+
+    if(mode == W100FB_SUSPEND_EXTMEM){
+
+	// CKE: Tri-State
+	val = readl(remapped_regs+mmMEM_EXT_CNTL);
+	val |= 0x40000000;    // bit30=1
+	writel(val, remapped_regs+mmMEM_EXT_CNTL);
+
+	// CLK: Stop
+	val = readl(remapped_regs+mmMEM_EXT_CNTL);
+	val &= ~(0x00000001);    // bit0=0
+	writel(val, remapped_regs+mmMEM_EXT_CNTL);
+    }else{
+
+	writel(0x00000000, remapped_regs+mmSCLK_CNTL);
+	writel(0x000000BF, remapped_regs+mmCLK_PIN_CNTL);
+	writel(0x00000015, remapped_regs+mmPWRMGT_CNTL);
+
+	udelay(5); // wait 5us
+
+	val = readl(remapped_regs+mmPLL_CNTL);
+	val |= 0x00000004; // bit2=1
+	writel(val, remapped_regs+mmPLL_CNTL);
+	writel(0x0000001d, remapped_regs+mmPWRMGT_CNTL);
+    }
+}
+
+
+static void w100fb_soft_reset()
+{
+    u16 val = readw((u16*)remapped_base+6);
+    writew(val|0x08, (u16*)remapped_base+6);
+    udelay(100);
+    writew(0x00, (u16*)remapped_base+6);
+    udelay(100);
+}
+
+static void w100fb_resume()
+{
+    u32    temp32;
+
+    w100fb_hw_init();
+    w100fb_PwmSetup();
+
+    temp32 = readl(remapped_regs+mmDISP_DEBUG2);
+    temp32 &= 0xff7fffff;
+    temp32 |= 0x00800000;
+    writel(temp32, remapped_regs+mmDISP_DEBUG2);
+
+	if (w100fb_lcdMode == LCD_MODE_480) {
+		w100fb_init_sharp_lcd(LCD_SHARP_VGA);
+	}
+	else {
+		w100fb_init_sharp_lcd(LCD_SHARP_QVGA);
+		if (w100fb_lcdMode == LCD_MODE_320) {
+			w100fb_init_qvga_rotation( (u16)270 );
+		}
+	}
+
+    w100fb_gamma_init();
+
+}
+
+static void w100fb_clear_screen(u32 mode,void *pfbuf)
+{
+  u16 *pVram = (u16 *)remapped_fbuf;
+  int i,numPix=0;
+
+  if(pfbuf != NULL)
+      pVram = pfbuf;
+
+  if(mode == LCD_SHARP_VGA){
+    numPix = 640*480;
+  }else if(mode == LCD_SHARP_QVGA){
+    numPix = 320*240;
+  }
+  for(i=0;i<numPix;i++)
+    pVram[i] = 0xffff;
+}
+
+#define W100FB_VSYNC_TIMEOUT 30000 // timeout = 30[ms] > 16.8[ms]
+//
+static void w100fb_vsync()
+{
+    u32 tmp;
+    int timeout = W100FB_VSYNC_TIMEOUT;
+
+    tmp = readl(remapped_regs+mmACTIVE_V_DISP);
+
+    // set vline pos 
+    writel((tmp>>16)&0x3ff,remapped_regs+mmDISP_INT_CNTL);
+
+    // disable vline irq
+    tmp = readl(remapped_regs+mmGEN_INT_CNTL);
+
+    tmp &= ~0x00000002;
+    writel(tmp,remapped_regs+mmGEN_INT_CNTL);
+
+    // clear vline irq status
+    writel(0x00000002,remapped_regs+mmGEN_INT_STATUS);
+
+    // enable vline irq
+    writel((tmp|0x00000002),remapped_regs+mmGEN_INT_CNTL);
+
+    // clear vline irq status
+    writel(0x00000002,remapped_regs+mmGEN_INT_STATUS);
+
+    while(timeout > 0)
+    {
+	if(readl(remapped_regs+mmGEN_INT_STATUS) & 0x00000002)
+	    break;
+	udelay(1);
+	timeout--;
+    }
+
+    // disable vline irq
+    writel(tmp,remapped_regs+mmGEN_INT_CNTL);
+
+    // clear vline irq status
+    writel(0x00000002,remapped_regs+mmGEN_INT_STATUS);
+}
+
+static void w100fb_InitExtMem(u32 mode)
+{
+    switch (mode)
+    {
+        case LCD_SHARP_QVGA:
+            // QVGA doesn't use external memory
+            // nothing to do, really.
+            break;
+        case LCD_SHARP_VGA:
+            writel(0x00007800, remapped_regs+mmMC_BIST_CTRL);
+            writel(0x00040003, remapped_regs+mmMEM_EXT_CNTL);			
+            writel(0x00200021, remapped_regs+mmMEM_SDRAM_MODE_REG);
+            w100fb_Delay(100);
+            writel(0x80200021, remapped_regs+mmMEM_SDRAM_MODE_REG);
+            w100fb_Delay(100);
+            writel(0x00650021, remapped_regs+mmMEM_SDRAM_MODE_REG);
+            w100fb_Delay(100);
+	    writel(0x10002a4a, remapped_regs+mmMEM_EXT_TIMING_CNTL);
+	    writel(0x7ff87012, remapped_regs+mmMEM_IO_CNTL);
+            break;
+        default:
+            // assume our Wallaby board memory
+            writel(0x00007800, remapped_regs+mmMC_BIST_CTRL);
+            writel(0x00040007, remapped_regs+mmMEM_EXT_CNTL);
+            writel(0x00200021, remapped_regs+mmMEM_SDRAM_MODE_REG);
+            w100fb_Delay(100);
+            writel(0x80200021, remapped_regs+mmMEM_SDRAM_MODE_REG);
+            w100fb_Delay(100);
+            writel(0x00650021, remapped_regs+mmMEM_SDRAM_MODE_REG);
+            w100fb_Delay(100);
+            writel(0x01002a5a, remapped_regs+mmMEM_EXT_TIMING_CNTL);
+            writel(0x7ff07001, remapped_regs+mmMEM_IO_CNTL);
+            break;
+    }
+}
+
+#define RESCTL_ADRS     0x00
+#define PHACTRL_ADRS	0x01
+#define DUTYCTRL_ADRS	0x02
+#define POWERREG0_ADRS	0x03
+#define POWERREG1_ADRS	0x04
+#define GPOR3_ADRS	0x05
+#define PICTRL_ADRS     0x06
+#define POLCTRL_ADRS    0x07
+
+#define RESCTL_QVGA     0x01
+#define RESCTL_VGA      0x00
+
+#define POWER1_VW_ON	0x01	/* VW Supply FET ON */
+#define POWER1_GVSS_ON	0x02	/* GVSS(-8V) Power Supply ON */
+#define POWER1_VDD_ON	0x04	/* VDD(8V),SVSS(-4V) Power Supply ON */
+
+#define POWER1_VW_OFF	0x00	/* VW Supply FET OFF */
+#define POWER1_GVSS_OFF	0x00	/* GVSS(-8V) Power Supply OFF */
+#define POWER1_VDD_OFF	0x00	/* VDD(8V),SVSS(-4V) Power Supply OFF */
+
+#define POWER0_COM_DCLK	0x01	/* COM Voltage DC Bias DAC Serial Data Clock */
+#define POWER0_COM_DOUT	0x02	/* COM Voltage DC Bias DAC Serial Data Out */
+#define POWER0_DAC_ON	0x04	/* DAC Power Supply ON */
+#define POWER0_COM_ON	0x08	/* COM Powewr Supply ON */
+#define POWER0_VCC5_ON	0x10	/* VCC5 Power Supply ON */
+
+#define POWER0_DAC_OFF	0x00	/* DAC Power Supply OFF */
+#define POWER0_COM_OFF	0x00	/* COM Powewr Supply OFF */
+#define POWER0_VCC5_OFF	0x00	/* VCC5 Power Supply OFF */
+
+
+#define POWER0_I2C_DATA 	(POWER0_DAC_ON /* DAC ON */ | \
+	POWER0_COM_OFF /* COM OFF */ | POWER0_VCC5_OFF /* VCC5 OFF */)
+
+#define PICTRL_INIT_STATE	0x01
+#define PICTRL_INIOFF		0x02
+#define PICTRL_POWER_DOWN	0x04
+#define PICTRL_COM_SIGNAL_OFF	0x08
+#define PICTRL_DAC_SIGNAL_OFF	0x10
+
+#define PICTRL_POWER_ACTIVE	(0)
+
+#define POLCTRL_SYNC_POL_FALL	0x01
+#define POLCTRL_EN_POL_FALL	0x02
+#define POLCTRL_DATA_POL_FALL	0x04
+#define POLCTRL_SYNC_ACT_H	0x08
+#define POLCTRL_EN_ACT_L	0x10
+
+#define POLCTRL_SYNC_POL_RISE	0x00
+#define POLCTRL_EN_POL_RISE	0x00
+#define POLCTRL_DATA_POL_RISE	0x00
+#define POLCTRL_SYNC_ACT_L	0x00
+#define POLCTRL_EN_ACT_H	0x00
+
+#define PHACTRL_PHASE_MANUAL	0x01
+
+#define LCDTG_I2C_WAIT (10) /* usec */
+
+#define PHAD_QVGA_DEFAULT_VAL (9)
+#define COMADJ_DEFAULT        (125)
+
+static void lcdtg_ssp_send(u8 adrs, u8 data)
+{
+    ssp_put_dac_val(((adrs & 0x07) << 5) | (data & 0x1f), CS_LZ9JG18);
+}
+
+static void lcdtg_i2c_start_sequence(u8 base_data)
+{
+    u8 base = base_data;
+
+    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DCLK|POWER0_COM_DOUT);
+    udelay(LCDTG_I2C_WAIT);
+    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DCLK);
+    udelay(LCDTG_I2C_WAIT);
+    lcdtg_ssp_send(POWERREG0_ADRS, base);
+    udelay(LCDTG_I2C_WAIT);
+}
+
+static void lcdtg_i2c_stop_sequence(u8 base_data)
+{
+    u8 base = base_data;
+
+    lcdtg_ssp_send(POWERREG0_ADRS, base);
+    udelay(LCDTG_I2C_WAIT);
+    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DCLK);
+    udelay(LCDTG_I2C_WAIT);
+    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DCLK|POWER0_COM_DOUT);
+    udelay(LCDTG_I2C_WAIT);
+}
+
+static void lcdtg_i2c_send_byte(u8 base_data,u8 data)
+{
+    int i;
+
+    u8 base = base_data;
+
+    for( i = 0; i < 8; i++ ){
+	if(data & 0x80){
+	    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DOUT);
+	    udelay(LCDTG_I2C_WAIT);
+	    lcdtg_ssp_send(POWERREG0_ADRS, 
+			   base|POWER0_COM_DOUT|POWER0_COM_DCLK);
+	    udelay(LCDTG_I2C_WAIT);
+	    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DOUT);
+	}else{
+	    lcdtg_ssp_send(POWERREG0_ADRS, base);
+	    udelay(LCDTG_I2C_WAIT);
+	    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DCLK);
+	    udelay(LCDTG_I2C_WAIT);
+	    lcdtg_ssp_send(POWERREG0_ADRS, base);
+	}
+	udelay(LCDTG_I2C_WAIT);
+	data <<= 1;
+    }
+}
+
+static void lcdtg_i2c_wait_ack(u8 base_data)
+{
+    u8 base = base_data;
+
+    lcdtg_ssp_send(POWERREG0_ADRS, base);
+    udelay(LCDTG_I2C_WAIT);
+    lcdtg_ssp_send(POWERREG0_ADRS, base|POWER0_COM_DCLK);
+    udelay(LCDTG_I2C_WAIT);
+    lcdtg_ssp_send(POWERREG0_ADRS, base);
+    udelay(LCDTG_I2C_WAIT);
+}
+
+static void lcdtg_set_common_voltage(u8 base_data,u8 data)
+{
+    /* Set Common Voltage to M62232FP via I2C */
+    lcdtg_i2c_start_sequence( base_data );
+    lcdtg_i2c_send_byte( base_data, 0x9c );
+    lcdtg_i2c_wait_ack( base_data );
+    lcdtg_i2c_send_byte( base_data, 0x00 );
+    lcdtg_i2c_wait_ack( base_data );
+    lcdtg_i2c_send_byte( base_data, data );
+    lcdtg_i2c_wait_ack( base_data );
+    lcdtg_i2c_stop_sequence( base_data );
+}
+
+static struct lcdtg_register_setting {
+    u8 adrs;
+    u8 data;
+    u32 wait;
+} lcdtg_power_on_table[] = {
+
+    /* Initialize Internal Logic & Port */
+    { PICTRL_ADRS, 
+      PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE |
+      PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF,
+      0 }, 
+
+    { POWERREG0_ADRS,
+      POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF | POWER0_COM_OFF | 
+      POWER0_VCC5_OFF,
+      0 },
+
+    { POWERREG1_ADRS,
+      POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF,
+      0 },
+
+    /* VDD(+8V),SVSS(-4V) ON */
+    { POWERREG1_ADRS,
+      POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON /* VDD ON */,
+      3000 },
+
+    /* DAC ON */
+    { POWERREG0_ADRS,
+      POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON /* DAC ON */ | 
+      POWER0_COM_OFF | POWER0_VCC5_OFF,
+      0 },
+
+    /* INIB = H, INI = L  */
+    { PICTRL_ADRS, 
+      /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
+      PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF,
+      0 }, 
+
+    /* Set Common Voltage */
+    { 0xfe, 0, 0 },
+
+    /* VCC5 ON */
+    { POWERREG0_ADRS,
+      POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON /* DAC ON */ | 
+      POWER0_COM_OFF | POWER0_VCC5_ON /* VCC5 ON */,
+      0 },
+
+    /* GVSS(-8V) ON */
+    { POWERREG1_ADRS,
+      POWER1_VW_OFF | POWER1_GVSS_ON /* GVSS ON */ | 
+      POWER1_VDD_ON /* VDD ON */,
+      2000 },
+
+    /* COM SIGNAL ON (PICTL[3] = L) */
+    { PICTRL_ADRS, 
+      PICTRL_INIT_STATE,
+      0 },
+
+    /* COM ON */
+    { POWERREG0_ADRS,
+      POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON /* DAC ON */ | 
+      POWER0_COM_ON /* COM ON */ | POWER0_VCC5_ON /* VCC5_ON */,
+      0 },
+
+    /* VW ON */
+    { POWERREG1_ADRS,
+      POWER1_VW_ON /* VW ON */ | POWER1_GVSS_ON /* GVSS ON */ | 
+      POWER1_VDD_ON /* VDD ON */,
+      0 /* Wait 100ms */ },
+
+    /* Signals output enable */
+    { PICTRL_ADRS, 
+      0 /* Signals output enable */,
+      0 },
+
+    { PHACTRL_ADRS,
+      PHACTRL_PHASE_MANUAL,
+      0 },
+
+    /* Initialize for Input Signals from ATI */
+    { POLCTRL_ADRS,
+      POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE | POLCTRL_DATA_POL_RISE |
+      POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H,
+      1000 /*100000*/ /* Wait 100ms */ },
+
+    /* end mark */
+    { 0xff, 0, 0 }
+};
+
+static void lcdtg_resume()
+{
+  if (w100fb_lcdMode == LCD_MODE_480) {
+	  lcdtg_hw_init(LCD_SHARP_VGA);
+  }
+  else {
+	  lcdtg_hw_init(LCD_SHARP_QVGA);
+  }
+  corgibl_pm_callback(NULL, PM_RESUME, NULL);
+}
+
+static void lcdtg_suspend()
+{
+    int i;
+    u16 *pVram = (u16*)remapped_fbuf;
+
+    for( i = 0; i < (current_par.xres * current_par.yres); i++ ) {
+	*pVram = 0xffff; // white color
+	pVram++;
+    }
+
+    // 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec
+    mdelay(34);
+
+    // (1) backlight off
+    corgibl_pm_callback(NULL, PM_SUSPEND, NULL);
+
+    // (2)VW OFF */  
+    lcdtg_ssp_send( POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON );	
+
+    // (4)COM OFF */  
+    lcdtg_ssp_send( PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF  );
+    lcdtg_ssp_send( POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON );
+
+    // (5)Set Common Voltage Bias 0V */
+    lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON ,0);
+
+    // (6)GVSS OFF */
+    lcdtg_ssp_send( POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON );
+
+    // (7)VCC5 OFF */
+    lcdtg_ssp_send( POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF );
+
+    // (8)Set PDWN, INIOFF, DACOFF */
+    lcdtg_ssp_send( PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF | 
+		    PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF  );
+
+    /* (9)Stop LCDC */
+//  W100SoftwareReset();
+
+    // (10)DAC OFF */
+    lcdtg_ssp_send( POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF );
+
+    // (11)VDD OFF */
+    lcdtg_ssp_send( POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF );
+
+}
+static void lcdtg_set_phadadj(u32 mode)
+{
+    int adj;
+
+    if(mode == LCD_SHARP_VGA){
+	// Setting for VGA
+	adj = -1;
+	adj = sharpsl_get_phadadj();
+	if ( adj < 0 ) {
+	    adj = PHACTRL_PHASE_MANUAL;
+	}else{
+	    adj = ((adj & 0x0f)<< 1)| PHACTRL_PHASE_MANUAL;
+	}
+    }else{
+	// Setting for QVGA
+	adj = (PHAD_QVGA_DEFAULT_VAL << 1)| PHACTRL_PHASE_MANUAL;
+    }
+    lcdtg_ssp_send( PHACTRL_ADRS, adj );
+}
+
+static void lcdtg_hw_init(u32 mode)
+{
+    int i;
+    int comadj;
+
+    i = 0;
+    while(lcdtg_power_on_table[i].adrs != 0xff){
+	if (lcdtg_power_on_table[i].adrs == 0xfe) {
+	    /* Set Common Voltage */
+	    comadj = -1;
+	    comadj = sharpsl_get_comadj();
+	    if ( comadj < 0 ) {
+		comadj = COMADJ_DEFAULT;
+	    }
+	    lcdtg_set_common_voltage( POWER0_I2C_DATA, comadj );
+	}else if(lcdtg_power_on_table[i].adrs == PHACTRL_ADRS){
+	    /* Set Phase Adjuct */
+	    lcdtg_set_phadadj(mode);
+	}else{
+	    /* Other */
+	    lcdtg_ssp_send( lcdtg_power_on_table[i].adrs,
+			    lcdtg_power_on_table[i].data );
+	}
+	if(lcdtg_power_on_table[i].wait != 0)
+	    udelay(lcdtg_power_on_table[i].wait);
+	i++;
+    }
+
+    switch(mode){
+    case LCD_SHARP_QVGA:
+	/* Set Lcd Resolution (QVGA) */
+	lcdtg_ssp_send( RESCTL_ADRS, RESCTL_QVGA );
+	break;
+    case LCD_SHARP_VGA:
+	/* Set Lcd Resolution (VGA) */
+	lcdtg_ssp_send( RESCTL_ADRS, RESCTL_VGA );
+	break;
+    default:
+	break;
+    }
+}
+
+static void lcdtg_lcd_change(u32 mode)
+{
+    /* Set Phase Adjuct */
+    lcdtg_set_phadadj(mode);
+
+    if(mode == LCD_SHARP_VGA)
+	/* Set Lcd Resolution (VGA) */
+	lcdtg_ssp_send( RESCTL_ADRS, RESCTL_VGA );
+    else if(mode == LCD_SHARP_QVGA)
+	/* Set Lcd Resolution (QVGA) */
+	lcdtg_ssp_send( RESCTL_ADRS, RESCTL_QVGA );
+}
+
+#ifdef _IMAGE_CACHE_SUPPORT //
+
+// vga only
+//#undef __PRINTK
+//#define __PRINTK(arg...) printk(arg)
+//#define __SUM
+static u32* save_image_cache(u32 *alloc_num)
+{
+  u32 *img_src=NULL;
+  u32 *img_dst=NULL;
+  u32 img_size=0;
+  u32 img_kmalloc_num=0;
+  int i,j;
+#ifdef __SUM
+  u32 sum=0;
+#endif 
+
+#if defined(CONFIG_ARCH_SHARP_SL)
+    // checking in mm/omm_kill.c
+    //disable_signal_to_mm = 1; //@DEBUG
+#endif
+
+  __PRINTK("save image cache\n");
+  img_src = (u32*)remapped_fbuf + IMG_CACHE_OFFSET_VGA/sizeof(u32);
+  img_size = IMG_CACHE_TOTAL_SIZE_VGA;
+
+  __PRINTK(" - remapped_fbuf = %x\n",(int)remapped_fbuf);
+  __PRINTK(" - img_src = %x\n",(int)img_src);
+  __PRINTK(" - img_size = %x\n",img_size);
+
+  img_kmalloc_num = (img_size+IMG_CACHE_MALLOC_SIZE)/IMG_CACHE_MALLOC_SIZE;
+  img_dst = kmalloc(img_kmalloc_num*sizeof(u32),GFP_KERNEL);
+  if(img_dst == NULL)
+    goto save_img_cache_err;
+
+  __PRINTK(" - img_kmalloc_num = %d\n",img_kmalloc_num);
+  __PRINTK(" - img_dst = %x\n",(int)img_dst);
+
+  for(i=0;i<img_kmalloc_num;i++) img_dst[i] = (u32)NULL;
+
+  for(i=0;i<img_kmalloc_num;i++){
+#if 1 //skip image data
+    if(i < start_skip_save_image_no || i > end_skip_save_image_no ||
+       start_skip_save_image_no < 0 || end_skip_save_image_no < 0){
+      img_dst[i] = (u32)kmalloc(IMG_CACHE_MALLOC_SIZE,GFP_KERNEL);
+    }else{
+      img_dst[i] = IMG_CACHE_SKIP_MARK;
+    }
+#else
+    img_dst[i] = (u32)kmalloc(IMG_CACHE_MALLOC_SIZE,GFP_KERNEL);
+#endif
+
+    __PRINTK(" - malloc[%d] = %x\n",i,(int)img_dst[i]);
+
+    if(img_dst[i] == (u32)NULL){
+      img_kmalloc_num = i;
+      for(i=0;i<img_kmalloc_num;i++){
+#if 1 //skip image data
+	if(img_dst[i] != IMG_CACHE_SKIP_MARK){
+	  kfree((void*)img_dst[i]);
+	}
+#else
+	kfree((void*)img_dst[i]);
+#endif
+	__PRINTK("-- error: free[%d]=%x,i\n",img_dst[i]);
+      }
+      goto save_img_cache_err;
+    }
+  }
+
+  __PRINTK(" - img_src = %x\n",(int)img_src);
+
+  for(i=0;i<img_kmalloc_num;i++){
+    u32 *dst = (u32*)img_dst[i];
+#if 1 //skip image data
+    if((u32)dst == IMG_CACHE_SKIP_MARK){
+      __PRINTK("...save_skip[%d] = %x\n",i,dst);
+      for(j=0;j<(IMG_CACHE_MALLOC_SIZE/sizeof(u32));j++){
+	img_src++;
+	img_size -= sizeof(u32);
+	if((int)img_size <= 0){
+	  i=img_kmalloc_num; // for break!
+	  break;
+	}
+      }
+      if(i==img_kmalloc_num)
+	break;
+      continue;
+    }
+    __PRINTK("...save_exec[%d] = %x\n",i,dst);
+#endif
+    for(j=0;j<(IMG_CACHE_MALLOC_SIZE/sizeof(u32));j++){
+      dst[j] = *img_src;
+#ifdef __SUM
+      sum+=*img_src;
+#endif
+      img_src++;
+      img_size -= sizeof(u32);
+      if((int)img_size <= 0){
+	i=img_kmalloc_num; // for break!
+	break;
+      }
+    }
+  }
+  __PRINTK(" - SUCCESS!!\n");
+#ifdef __SUM
+  __PRINTK(" - SUM=%x\n",(int)sum);
+#endif
+
+  *alloc_num = img_kmalloc_num;
+
+#if defined(CONFIG_ARCH_SHARP_SL)
+    // checking in mm/omm_kill.c
+  //disable_signal_to_mm = 0; //@DEBUG
+  //disable_signal_to_mm = 1; //@DEBUG
+#endif
+
+  return img_dst;
+
+//
+ save_img_cache_err:
+  __PRINTK(" - ERROR!!\n");
+  if(img_dst){
+    kfree(img_dst);
+  }
+  *alloc_num = 0;
+
+#if defined(CONFIG_ARCH_SHARP_SL)
+    // checking in mm/omm_kill.c
+  // disable_signal_to_mm = 0; //@DEBUG
+  //  disable_signal_to_mm = 1; //@DEBUG
+#endif
+
+  return NULL;
+}
+
+//#undef __PRINTK
+//#define __PRINTK(arg...) printk(arg)
+
+static int restore_image_cache(u32 *img_src,u32 alloc_num)
+{
+  u32 *img_dst=NULL;
+  u32 img_size=0;
+  int i,j;
+#ifdef __SUM
+  u32 sum=0;
+#endif
+
+  if(img_src == NULL)
+    return -1; //ERROR
+
+  if(alloc_num == 0)
+    return -2; //ERROR
+
+  __PRINTK("restore image cache\n");
+  img_dst = (u32*)remapped_fbuf + IMG_CACHE_OFFSET_VGA/sizeof(u32);
+  img_size = IMG_CACHE_TOTAL_SIZE_VGA;
+
+  __PRINTK(" - remapped_fbuf = %x\n",(int)remapped_fbuf);
+  __PRINTK(" - img_src = %x\n",(int)img_src);
+  __PRINTK(" - img_dst = %x\n",(int)img_dst);
+
+  for(i=0;i<alloc_num;i++){
+    u32 *src = (u32*)img_src[i];
+#if 1 //skip image data
+    if((u32)src == IMG_CACHE_SKIP_MARK){
+      __PRINTK("...restore_skip[%d] = %x\n",i,src);
+      for(j=0;j<(IMG_CACHE_MALLOC_SIZE/sizeof(u32));j++){
+	img_dst++;
+	img_size -= sizeof(u32);
+	if((int)img_size <= 0){
+	  i=alloc_num; // for break!
+	  break;
+	}
+      }
+      if(i==alloc_num)
+	break;
+      continue;
+    }
+    __PRINTK("...restore_exec[%d] = %x\n",i,src);
+#else
+    __PRINTK(" -- %d:[%x]\n",i,img_src[i]);
+#endif
+
+    for(j=0;j<(IMG_CACHE_MALLOC_SIZE/sizeof(u32));j++){
+	*img_dst = src[j];
+#ifdef __SUM
+	sum+=*img_dst;
+#endif
+	img_dst++;
+	img_size -= sizeof(u32);
+	if((int)img_size <= 0){
+	  i=alloc_num; // for break!
+	  break;
+	}
+    }
+    //__PRINTK(" - free[%d] = %x\n",i,src);
+    //kfree(src);
+  }
+
+  __PRINTK(" - restore finished !!\n");
+
+  for(i=0;i<alloc_num;i++){
+    __PRINTK(" - free[%d] = %x\n",i,img_src[i]);
+#if 1 //skip image data
+    if(img_src[i] != IMG_CACHE_SKIP_MARK)
+      kfree((void*)img_src[i]);
+#else
+    kfree((void*)img_src[i]);
+#endif
+  }
+
+  __PRINTK(" - free[img_src] = %x\n",(int)img_src);
+  kfree((void*)img_src);
+
+  __PRINTK(" - SUCCESS!!\n");
+#ifdef __SUM
+  __PRINTK(" - SUM=%x\n",sum);
+#endif
+
+#if 1 //skip image data
+  start_skip_save_image_no = (-1);
+  end_skip_save_image_no = (-1);
+#endif 
+  return 0; //SUCCESS
+}
+
+static int cleanup_image_cache(u32 *img_src,u32 alloc_num)
+{
+  int i;
+
+  if(img_src == NULL)
+    return -1; //ERROR
+
+  if(alloc_num == 0)
+    return -2; //ERROR
+
+  __PRINTK("cleanup image cache \n");
+  __PRINTK(" - img_src = %x\n",(int)img_src);
+
+  for(i=0;i<alloc_num;i++){
+    __PRINTK(" -- %d:[%x]\n",i,img_src[i]);
+#if 1 //skip image data
+    if(img_src[i] != IMG_CACHE_SKIP_MARK)
+      kfree((void*)img_src[i]);
+#else
+    kfree((void*)img_src[i]);
+#endif
+  }
+  kfree((void*)img_src);
+
+  return 0; //SUCCESS
+}
+#endif //_IMAGE_CACHE_SUPPORT
+
+static void w100fb_pm_suspend(int suspend_mode)
+{
+    int i, j;
+    u16 *pVram = (u16*)remapped_fbuf;
+
+    if(suspend_mode == 1){
+	// called from blank()
+	isSuspended_tg_only = 1;
+    }else{
+	if(isSuspended_tg_only){
+	    // suspend w100 only.
+	    w100fb_suspend(W100FB_SUSPEND_ALL);
+	    isSuspended_tg_only = 0;
+	    return;
+	}
+	isSuspended_tg_only = 0;
+    }
+
+	for (i = 0; i < current_par.yres; i++) {
+		if (gSaveImagePtr[i] != NULL){
+			kfree(gSaveImagePtr[i]);
+			gSaveImagePtr[i] = NULL;
+		}
+		gSaveImagePtr[i] = kmalloc(current_par.xres * BITS_PER_PIXEL / 8, GFP_KERNEL);
+		if (gSaveImagePtr[i] != NULL){
+			for (j = 0; j < (current_par.xres); j++)
+				*(gSaveImagePtr[i] + j) = *(pVram++);
+		}
+		else {
+			printk("can't alloc pre-off image buffer %d\n", i);
+			for (j = 0; j < i; j++) {
+				if (gSaveImagePtr[i] != NULL) {
+					kfree(gSaveImagePtr[i]);
+					gSaveImagePtr[i] = NULL;
+				}
+			}
+			break;
+		}
+	}
+	for (; i < 640; i++) {
+		gSaveImagePtr[i] = NULL;
+	}
+
+#ifdef _IMAGE_CACHE_SUPPORT // FOR SUSPEND
+//#undef __PRINTK
+//#define __PRINTK(arg...) //printk(arg)
+	// VGA only
+	if(w100fb_lcdMode == LCD_MODE_480){
+	  __PRINTK("SUSPEND: save image cache ... ");
+	  if(save_img_alloc_num != 0 || save_img_cache_ptr != NULL){
+	    __PRINTK("ERROR!\n");
+	  }else{
+	    save_img_cache_ptr = save_image_cache(&save_img_alloc_num);
+
+	    if(save_img_alloc_num == 0 || save_img_cache_ptr == NULL){
+	      __PRINTK("ERROR!!\n");
+	    }else{
+	      __PRINTK("SUCCESS!\n");
+	    }
+	  }
+	}
+#endif //_IMAGE_CACHE_SUPPORT
+
+    lcdtg_suspend();
+
+    if(suspend_mode == 1){
+	// w100 suspend skip ...
+	return;
+    }
+
+    w100fb_suspend(W100FB_SUSPEND_ALL);
+}
+
+static void w100fb_pm_resume(int resume_mode)
+{
+    int i, j;
+    u16 *pVram = (u16*)remapped_fbuf;
+
+    if(resume_mode != 1 || !isSuspended_tg_only){
+	w100fb_resume();
+    }
+    else{
+    }
+    isSuspended_tg_only = 0;
+
+    if (gSaveImagePtr[0] != NULL){
+		for (i = 0; i < (current_par.yres); i++) {
+			if (gSaveImagePtr[i] == NULL) {
+				printk("can't find pre-off image buffer %d\n", i);
+				continue;
+			}
+			for (j = 0; j < (current_par.xres); j++) {
+				*(pVram++) = *(gSaveImagePtr[i] + j);
+			}
+			kfree(gSaveImagePtr[i]);
+			gSaveImagePtr[i] = NULL;
+		}
+    }
+
+#ifdef _IMAGE_CACHE_SUPPORT // FOR RESUME
+//#undef __PRINTK
+//#define __PRINTK(arg...) //printk(arg)
+    // VGA only
+    if(w100fb_lcdMode == LCD_MODE_480){
+      __PRINTK("RESUME: restore image cache ... ");
+      if(save_img_alloc_num == 0 || save_img_cache_ptr == NULL){
+	__PRINTK("ERROR!\n");
+      }else{
+	if(restore_image_cache(save_img_cache_ptr,
+			     save_img_alloc_num)){
+	  __PRINTK("ERROR!!\n");
+	}else{
+	  save_img_alloc_num=0;
+	  save_img_cache_ptr=NULL;
+	  __PRINTK("SUCCESS!\n");
+	}
+      }
+    }
+#endif //_IMAGE_CACHE_SUPPORT
+
+    lcdtg_resume();
+
+}
+
+#ifdef CONFIG_PM
+static int w100fb_pm_callback(struct pm_dev* pm_dev,
+			    pm_request_t req, void* data)
+{
+	switch (req) {
+	case PM_SUSPEND:
+		if (!w100fb_isblank) {
+		    w100fb_pm_suspend( 0 );
+		    fb_blank_normal = 0;
+
+		}
+		break;
+		
+	case PM_RESUME:
+		w100fb_pm_resume( 0 );
+		fb_blank_normal = 0;
+		w100fb_isblank = 0;
+		break;
+		
+	}
+
+	return 0;
+}
+
+void w100fb_fatal_off(void)
+{
+  lcdtg_suspend();
+  w100fb_resume();
+  w100fb_suspend(W100FB_SUSPEND_ALL);
+}
+#endif //CONFIG_PM
+
+module_init(w100fb_init);
+#ifdef MODULE
+module_exit(w100fb_cleanup);
+#endif
--- /dev/null
+++ linux-2.6.10-rc1/drivers/video/w100fb.h
@@ -0,0 +1,4338 @@
+/*
+ * linux/drivers/video/w100fb.h
+ *
+ * Frame Buffer Device for ATI w100 (Wallaby)
+ *
+ * Copyright (C) 2002, ATI Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * ChangeLog:
+ *
+ */
+
+#if !defined (_W100FB_H)
+#define _W100FB_H
+
+/* Block CIF Start: */
+#define mmCHIP_ID                                                    0x0000
+#define mmREVISION_ID                                                0x0004
+#define mmWRAP_BUF_A                                                 0x0008
+#define mmWRAP_BUF_B                                                 0x000C
+#define mmWRAP_TOP_DIR                                               0x0010
+#define mmWRAP_START_DIR                                             0x0014
+#define mmCIF_CNTL                                                   0x0018
+#define mmCFGREG_BASE                                                0x001C
+#define mmCIF_IO                                                     0x0020
+#define mmCIF_READ_DBG                                               0x0024
+#define mmCIF_WRITE_DBG                                              0x0028
+#define cfgIND_ADDR_A_0                                              0x0000
+#define cfgIND_ADDR_A_1                                              0x0001
+#define cfgIND_ADDR_A_2                                              0x0002
+#define cfgIND_DATA_A                                                0x0003
+#define cfgREG_BASE                                                  0x0004
+#define cfgINTF_CNTL                                                 0x0005
+#define cfgSTATUS                                                    0x0006
+#define cfgCPU_DEFAULTS                                              0x0007
+#define cfgIND_ADDR_B_0                                              0x0008
+#define cfgIND_ADDR_B_1                                              0x0009
+#define cfgIND_ADDR_B_2                                              0x000A
+#define cfgIND_DATA_B                                                0x000B
+#define cfgPM4_RPTR                                                  0x000C
+#define cfgSCRATCH                                                   0x000D
+#define cfgPM4_WRPTR_0                                               0x000E
+#define cfgPM4_WRPTR_1                                               0x000F
+/* Block CIF End: */
+
+/* Block CP Start: */
+#define mmCP_RB_CNTL                                                 0x0210
+#define mmCP_RB_BASE                                                 0x0214
+#define mmCP_RB_RPTR_ADDR                                            0x0218
+#define mmCP_RB_RPTR                                                 0x021C
+#define mmCP_RB_RPTR_WR                                              0x02F8
+#define mmCP_RB_WPTR                                                 0x0220
+#define mmCP_IB_BASE                                                 0x0228
+#define mmCP_IB_BUFSZ                                                0x022C
+#define mmCP_CSQ_CNTL                                                0x0230
+#define mmCP_CSQ_APER_PRIMARY                                        0x0300
+#define mmCP_CSQ_APER_INDIRECT                                       0x0340
+#define mmCP_ME_CNTL                                                 0x0240
+#define mmCP_ME_RAM_ADDR                                             0x0244
+#define mmCP_ME_RAM_RADDR                                            0x0248
+#define mmCP_ME_RAM_DATAH                                            0x024C
+#define mmCP_ME_RAM_DATAL                                            0x0250
+#define mmCP_DEBUG                                                   0x025C
+#define mmSCRATCH_REG0                                               0x0260
+#define mmSCRATCH_REG1                                               0x0264
+#define mmSCRATCH_REG2                                               0x0268
+#define mmSCRATCH_REG3                                               0x026C
+#define mmSCRATCH_REG4                                               0x0270
+#define mmSCRATCH_REG5                                               0x0274
+#define mmSCRATCH_UMSK                                               0x0280
+#define mmSCRATCH_ADDR                                               0x0284
+#define mmCP_CSQ_ADDR                                                0x02E4
+#define mmCP_CSQ_DATA                                                0x02E8
+#define mmCP_CSQ_STAT                                                0x02EC
+#define mmCP_STAT                                                    0x02F0
+#define mmGEN_INT_CNTL                                               0x0200
+#define mmGEN_INT_STATUS                                             0x0204
+/* Block CP End: */
+
+/* Block DISPLAY Start: */
+#define mmLCD_FORMAT                                                 0x0410
+#define mmGRAPHIC_CTRL                                               0x0414
+#define mmGRAPHIC_OFFSET                                             0x0418
+#define mmGRAPHIC_PITCH                                              0x041C
+#define mmCRTC_TOTAL                                                 0x0420
+#define mmACTIVE_H_DISP                                              0x0424
+#define mmACTIVE_V_DISP                                              0x0428
+#define mmGRAPHIC_H_DISP                                             0x042C
+#define mmGRAPHIC_V_DISP                                             0x0430
+#define mmVIDEO_CTRL                                                 0x0434
+#define mmGRAPHIC_KEY                                                0x0438
+#define mmVIDEO_Y_OFFSET                                             0x043C
+#define mmVIDEO_Y_PITCH                                              0x0440
+#define mmVIDEO_U_OFFSET                                             0x0444
+#define mmVIDEO_U_PITCH                                              0x0448
+#define mmVIDEO_V_OFFSET                                             0x044C
+#define mmVIDEO_V_PITCH                                              0x0450
+#define mmVIDEO_H_POS                                                0x0454
+#define mmVIDEO_V_POS                                                0x0458
+#define mmBRIGHTNESS_CNTL                                            0x045C
+#define mmCURSOR1_OFFSET                                             0x0460
+#define mmCURSOR1_H_POS                                              0x0464
+#define mmCURSOR1_V_POS                                              0x0468
+#define mmCURSOR1_COLOR0                                             0x046C
+#define mmCURSOR1_COLOR1                                             0x0470
+#define mmCURSOR2_OFFSET                                             0x0474
+#define mmCURSOR2_H_POS                                              0x0478
+#define mmCURSOR2_V_POS                                              0x047C
+#define mmCURSOR2_COLOR0                                             0x0480
+#define mmCURSOR2_COLOR1                                             0x0484
+#define mmDISP_INT_CNTL                                              0x0488
+#define mmCRTC_SS                                                    0x048C
+#define mmCRTC_LS                                                    0x0490
+#define mmCRTC_REV                                                   0x0494
+#define mmCRTC_DCLK                                                  0x049C
+#define mmCRTC_GS                                                    0x04A0
+#define mmCRTC_VPOS_GS                                               0x04A4
+#define mmCRTC_GCLK                                                  0x04A8
+#define mmCRTC_GOE                                                   0x04AC
+#define mmCRTC_FRAME                                                 0x04B0
+#define mmCRTC_FRAME_VPOS                                            0x04B4
+#define mmGPIO_DATA                                                  0x04B8
+#define mmGPIO_CNTL1                                                 0x04BC
+#define mmGPIO_CNTL2                                                 0x04C0
+#define mmLCDD_CNTL1                                                 0x04C4
+#define mmLCDD_CNTL2                                                 0x04C8
+#define mmGENLCD_CNTL1                                               0x04CC
+#define mmGENLCD_CNTL2                                               0x04D0
+#define mmDISP_DEBUG                                                 0x04D4
+#define mmDISP_DB_BUF_CNTL                                           0x04D8
+#define mmDISP_CRC_SIG                                               0x04DC
+#define mmCRTC_DEFAULT_COUNT                                         0x04E0
+#define mmLCD_BACKGROUND_COLOR                                       0x04E4
+#define mmCRTC_PS2                                                   0x04E8
+#define mmCRTC_PS2_VPOS                                              0x04EC
+#define mmCRTC_PS1_ACTIVE                                            0x04F0
+#define mmCRTC_PS1_NACTIVE                                           0x04F4
+#define mmCRTC_GCLK_EXT                                              0x04F8
+#define mmCRTC_ALW                                                   0x04FC
+#define mmCRTC_ALW_VPOS                                              0x0500
+#define mmCRTC_PSK                                                   0x0504
+#define mmCRTC_PSK_HPOS                                              0x0508
+#define mmCRTC_CV4_START                                             0x050C
+#define mmCRTC_CV4_END                                               0x0510
+#define mmCRTC_CV4_HPOS                                              0x0514
+#define mmCRTC_ECK                                                   0x051C
+#define mmREFRESH_CNTL                                               0x0520
+#define mmGENLCD_CNTL3                                               0x0524
+#define mmGPIO_DATA2                                                 0x0528
+#define mmGPIO_CNTL3                                                 0x052C
+#define mmGPIO_CNTL4                                                 0x0530
+#define mmCHIP_STRAP                                                 0x0534
+#define mmDISP_DEBUG2                                                0x0538
+#define mmDEBUG_BUS_CNTL                                             0x053C
+#define mmGAMMA_VALUE1                                               0x0540
+#define mmGAMMA_VALUE2                                               0x0544
+#define mmGAMMA_SLOPE                                                0x0548
+#define mmGEN_STATUS                                                 0x054C
+#define mmHW_INT                                                     0x0550
+/* Block DISPLAY End: */
+
+/* Block GFX Start: */
+#define mmDST_OFFSET                                                 0x1004
+#define mmDST_PITCH                                                  0x1008
+#define mmDST_PITCH_OFFSET                                           0x102C
+#define mmDST_X                                                      0x101C
+#define mmDST_Y                                                      0x1020
+#define mmDST_X_Y                                                    0x1194
+#define mmDST_Y_X                                                    0x1038
+#define mmDST_WIDTH                                                  0x100C
+#define mmDST_HEIGHT                                                 0x1010
+#define mmDST_WIDTH_HEIGHT                                           0x1198
+#define mmDST_HEIGHT_WIDTH                                           0x103C
+#define mmDST_HEIGHT_WIDTH_8                                         0x118C
+#define mmDST_HEIGHT_Y                                               0x11A0
+#define mmDST_WIDTH_X                                                0x1188
+#define mmDST_WIDTH_X_INCY                                           0x119C
+#define mmDST_LINE_START                                             0x1090
+#define mmDST_LINE_END                                               0x1094
+#define mmBRUSH_OFFSET                                               0x108C
+#define mmBRUSH_Y_X                                                  0x1074
+#define mmDP_BRUSH_FRGD_CLR                                          0x107C
+#define mmDP_BRUSH_BKGD_CLR                                          0x1078
+#define mmSRC2_OFFSET                                                0x1060
+#define mmSRC2_PITCH                                                 0x1064
+#define mmSRC2_PITCH_OFFSET                                          0x1068
+#define mmSRC2_X                                                     0x1050
+#define mmSRC2_Y                                                     0x1054
+#define mmSRC2_X_Y                                                   0x1058
+#define mmSRC2_WIDTH                                                 0x1080
+#define mmSRC2_HEIGHT                                                0x1084
+#define mmSRC2_INC                                                   0x1088
+#define mmSRC_OFFSET                                                 0x11AC
+#define mmSRC_PITCH                                                  0x11B0
+#define mmSRC_PITCH_OFFSET                                           0x1028
+#define mmSRC_X                                                      0x1014
+#define mmSRC_Y                                                      0x1018
+#define mmSRC_X_Y                                                    0x1190
+#define mmSRC_Y_X                                                    0x1034
+#define mmSRC_WIDTH                                                  0x1040
+#define mmSRC_HEIGHT                                                 0x1044
+#define mmSRC_INC                                                    0x1048
+#define mmHOST_DATA0                                                 0x13C0
+#define mmHOST_DATA1                                                 0x13C4
+#define mmHOST_DATA2                                                 0x13C8
+#define mmHOST_DATA3                                                 0x13CC
+#define mmHOST_DATA4                                                 0x13D0
+#define mmHOST_DATA5                                                 0x13D4
+#define mmHOST_DATA6                                                 0x13D8
+#define mmHOST_DATA7                                                 0x13DC
+#define mmHOST_DATA_LAST                                             0x13E0
+#define mmDP_SRC_FRGD_CLR                                            0x1240
+#define mmDP_SRC_BKGD_CLR                                            0x1244
+#define mmSC_LEFT                                                    0x1140
+#define mmSC_RIGHT                                                   0x1144
+#define mmSC_TOP                                                     0x1148
+#define mmSC_BOTTOM                                                  0x114C
+#define mmSRC_SC_RIGHT                                               0x1154
+#define mmSRC_SC_BOTTOM                                              0x115C
+#define mmDP_CNTL                                                    0x11C8
+#define mmDP_CNTL_DST_DIR                                            0x11CC
+#define mmDP_DATATYPE                                                0x12C4
+#define mmDP_MIX                                                     0x12C8
+#define mmDP_WRITE_MSK                                               0x12CC
+#define mmCLR_CMP_CLR_SRC                                            0x1234
+#define mmCLR_CMP_CLR_DST                                            0x1238
+#define mmCLR_CMP_CNTL                                               0x1230
+#define mmCLR_CMP_MSK                                                0x123C
+#define mmDEFAULT_PITCH_OFFSET                                       0x10A0
+#define mmDEFAULT_SC_BOTTOM_RIGHT                                    0x10A8
+#define mmDEFAULT2_SC_BOTTOM_RIGHT                                   0x10AC
+#define mmREF1_PITCH_OFFSET                                          0x10B8
+#define mmREF2_PITCH_OFFSET                                          0x10BC
+#define mmREF3_PITCH_OFFSET                                          0x10C0
+#define mmREF4_PITCH_OFFSET                                          0x10C4
+#define mmREF5_PITCH_OFFSET                                          0x10C8
+#define mmREF6_PITCH_OFFSET                                          0x10CC
+#define mmDP_GUI_MASTER_CNTL                                         0x106C
+#define mmSC_TOP_LEFT                                                0x11BC
+#define mmSC_BOTTOM_RIGHT                                            0x11C0
+#define mmSRC_SC_BOTTOM_RIGHT                                        0x11C4
+#define mmGLOBAL_ALPHA                                               0x1210
+#define mmFILTER_COEF                                                0x1214
+#define mmMVC_CNTL_START                                             0x11E0
+#define mmE2_ARITHMETIC_CNTL                                         0x1220
+#define mmDEBUG0                                                     0x1280
+#define mmDEBUG1                                                     0x1284
+#define mmDEBUG2                                                     0x1288
+#define mmDEBUG3                                                     0x128C
+#define mmDEBUG4                                                     0x1290
+#define mmDEBUG5                                                     0x1294
+#define mmDEBUG6                                                     0x1298
+#define mmDEBUG7                                                     0x129C
+#define mmDEBUG8                                                     0x12A0
+#define mmDEBUG9                                                     0x12A4
+#define mmDEBUG10                                                    0x12A8
+#define mmDEBUG11                                                    0x12AC
+#define mmDEBUG12                                                    0x12B0
+#define mmDEBUG13                                                    0x12B4
+#define mmDEBUG14                                                    0x12B8
+#define mmDEBUG15                                                    0x12BC
+#define mmENG_CNTL                                                   0x13E8
+#define mmENG_PERF_CNT                                               0x13F0
+/* Block GFX End: */
+
+/* Block IDCT Start: */
+#define mmIDCT_RUNS                                                  0x0C00
+#define mmIDCT_LEVELS                                                0x0C04
+#define mmIDCT_CONTROL                                               0x0C3C
+#define mmIDCT_AUTH_CONTROL                                          0x0C08
+#define mmIDCT_AUTH                                                  0x0C0C
+/* Block IDCT End: */
+
+/* Block MC Start: */
+#define mmMEM_CNTL                                                   0x0180
+#define mmMEM_ARB                                                    0x0184
+#define mmMC_FB_LOCATION                                             0x0188
+#define mmMEM_EXT_CNTL                                               0x018C
+#define mmMC_EXT_MEM_LOCATION                                        0x0190
+#define mmMEM_EXT_TIMING_CNTL                                        0x0194
+#define mmMEM_SDRAM_MODE_REG                                         0x0198
+#define mmMEM_IO_CNTL                                                0x019C
+#define mmMC_DEBUG                                                   0x01A0
+#define mmMC_BIST_CTRL                                               0x01A4
+#define mmMC_BIST_COLLAR_READ                                        0x01A8
+#define mmTC_MISMATCH                                                0x01AC
+#define mmMC_PERF_MON_CNTL                                           0x01B0
+#define mmMC_PERF_COUNTERS                                           0x01B4
+/* Block MC End: */
+
+/* Block RBBM Start: */
+#define mmWAIT_UNTIL                                                 0x1400
+#define mmISYNC_CNTL                                                 0x1404
+#define mmRBBM_GUICNTL                                               0x1408
+#define mmRBBM_STATUS                                                0x0140
+#define mmRBBM_STATUS_alt_1                                          0x140C
+#define mmRBBM_CNTL                                                  0x0144
+#define mmRBBM_SOFT_RESET                                            0x0148
+#define mmNQWAIT_UNTIL                                               0x0150
+#define mmRBBM_DEBUG                                                 0x016C
+#define mmRBBM_CMDFIFO_ADDR                                          0x0170
+#define mmRBBM_CMDFIFO_DATAL                                         0x0174
+#define mmRBBM_CMDFIFO_DATAH                                         0x0178
+#define mmRBBM_CMDFIFO_STAT                                          0x017C
+/* Block RBBM End: */
+
+/* Block CG Start: */
+#define mmCLK_PIN_CNTL                                               0x0080
+#define mmPLL_REF_FB_DIV                                             0x0084
+#define mmPLL_CNTL                                                   0x0088
+#define mmSCLK_CNTL                                                  0x008C
+#define mmPCLK_CNTL                                                  0x0090
+#define mmCLK_TEST_CNTL                                              0x0094
+#define mmPWRMGT_CNTL                                                0x0098
+#define mmPWRMGT_STATUS                                              0x009C
+/* Block CG End: */
+
+/* default value definitions */
+#define defCHIP_ID                        0x00001002
+#define defREVISION_ID                    0x00000000
+#define defWRAP_BUF_A                     0x01000000
+#define defWRAP_BUF_B                     0x01000000
+#define defWRAP_TOP_DIR                   0x00000000
+#define defWRAP_START_DIR                 0x00000000
+//#define defCIF_CNTL                       0x00082900
+#define defCIF_CNTL                       0x00182d00		//??updated by Tobey Z.for Sharp,Oct11,2002
+#define defCFGREG_BASE                    0x00000000
+//#define defCIF_IO                         0x000c0800
+#define defCIF_IO                         0x000C0902		//??updated by Tobey Z.for Sharp,Oct11,2002
+#define defCIF_READ_DBG                   0x00018223
+#define defCIF_WRITE_DBG                  0x00002100
+#define defIND_ADDR_A_0                   0x00000000
+#define defIND_ADDR_A_1                   0x00000000
+#define defIND_ADDR_A_2                   0x00000000
+#define defIND_DATA_A                     0x00000000
+#define defREG_BASE                       0x00000001
+#define defINTF_CNTL                      0x00000011
+#define defSTATUS                         0x00000000
+#define defCPU_DEFAULTS                   0x00000006
+#define defIND_ADDR_B_0                   0x00000000
+#define defIND_ADDR_B_1                   0x00000000
+#define defIND_ADDR_B_2                   0x00000000
+#define defIND_DATA_B                     0x00000000
+#define defPM4_RPTR                       0x00000000
+#define defSCRATCH                        0x00000000
+#define defPM4_WRPTR_0                    0x00000000
+#define defPM4_WRPTR_1                    0x00000000
+#define defCP_RB_CNTL                     0x00000000
+#define defCP_RB_BASE                     0x00000000
+#define defCP_RB_RPTR_ADDR                0x00000000
+#define defCP_RB_RPTR                     0x00000000
+#define defCP_RB_RPTR_WR                  0x00000000
+#define defCP_RB_WPTR                     0x00000000
+#define defCP_IB_BASE                     0x00000000
+#define defCP_IB_BUFSZ                    0x00000000
+#define defCP_CSQ_CNTL                    0x00000000
+#define defCP_CSQ_APER_PRIMARY            0x00000000
+#define defCP_CSQ_APER_INDIRECT           0x00000000
+#define defCP_ME_CNTL                     0x40000000
+#define defCP_ME_RAM_ADDR                 0x00000000
+#define defCP_ME_RAM_RADDR                0x00000000
+#define defCP_ME_RAM_DATAH                0x00000000
+#define defCP_ME_RAM_DATAL                0x00000000
+#define defCP_DEBUG                       0x00000000
+#define defSCRATCH_REG0                   0x00000000
+#define defSCRATCH_REG1                   0x00000000
+#define defSCRATCH_REG2                   0x00000000
+#define defSCRATCH_REG3                   0x00000000
+#define defSCRATCH_REG4                   0x00000000
+#define defSCRATCH_REG5                   0x00000000
+#define defSCRATCH_UMSK                   0x00000000
+#define defSCRATCH_ADDR                   0x00000000
+#define defCP_CSQ_ADDR                    0x00000000
+#define defCP_CSQ_DATA                    0x00000000
+#define defCP_CSQ_STAT                    0x00000000
+#define defCP_STAT                        0x00000000
+#define defGEN_INT_CNTL                   0x00000000
+#define defGEN_INT_STATUS_rd              0x00080000
+#define defGEN_INT_STATUS_wr              0x00000000
+#define defLCD_FORMAT                     0x00000000
+#define defGRAPHIC_CTRL                   0x00000000
+#define defGRAPHIC_OFFSET                 0x00000000
+#define defGRAPHIC_PITCH                  0x00000000
+#define defCRTC_TOTAL                     0x00000000
+#define defACTIVE_H_DISP                  0x00000000
+#define defACTIVE_V_DISP                  0x00000000
+#define defGRAPHIC_H_DISP                 0x00000000
+#define defGRAPHIC_V_DISP                 0x00000000
+#define defVIDEO_CTRL                     0x00000000
+#define defGRAPHIC_KEY                    0x00000000
+#define defVIDEO_Y_OFFSET                 0x00000000
+#define defVIDEO_Y_PITCH                  0x00000000
+#define defVIDEO_U_OFFSET                 0x00000000
+#define defVIDEO_U_PITCH                  0x00000000
+#define defVIDEO_V_OFFSET                 0x00000000
+#define defVIDEO_V_PITCH                  0x00000000
+#define defVIDEO_H_POS                    0x00000000
+#define defVIDEO_V_POS                    0x00000000
+#define defBRIGHTNESS_CNTL                0x00000000
+#define defCURSOR1_OFFSET                 0x00000000
+#define defCURSOR1_H_POS                  0x00000000
+#define defCURSOR1_V_POS                  0x00000000
+#define defCURSOR1_COLOR0                 0x00000000
+#define defCURSOR1_COLOR1                 0x00000000
+#define defCURSOR2_OFFSET                 0x00000000
+#define defCURSOR2_H_POS                  0x00000000
+#define defCURSOR2_V_POS                  0x00000000
+#define defCURSOR2_COLOR0                 0x00000000
+#define defCURSOR2_COLOR1                 0x00000000
+#define defDISP_INT_CNTL                  0x00000000
+#define defCRTC_SS                        0x00000000
+#define defCRTC_LS                        0x00000000
+#define defCRTC_REV                       0x00000000
+#define defCRTC_DCLK                      0x00000000
+#define defCRTC_GS                        0x00000000
+#define defCRTC_VPOS_GS                   0x00000000
+#define defCRTC_GCLK                      0x00000000
+#define defCRTC_GOE                       0x00000000
+#define defCRTC_FRAME                     0x00000000
+#define defCRTC_FRAME_VPOS                0x00000000
+#define defGPIO_DATA                      0x00000000
+#define defGPIO_CNTL1                     0xff00ff00
+#define defGPIO_CNTL2                     0x00000000
+#define defLCDD_CNTL1                     0x0000ffff
+#define defLCDD_CNTL2                     0x00000000
+#define defGENLCD_CNTL1                   0x00aaa002
+#define defGENLCD_CNTL2                   0x00000002
+#define defDISP_DEBUG                     0x00000000
+#define defDISP_DB_BUF_CNTL_rd            0x00000000
+#define defDISP_DB_BUF_CNTL_wr            0x00000000
+#define defDISP_CRC_SIG                   0x00000000
+#define defCRTC_DEFAULT_COUNT             0x00000000
+#define defLCD_BACKGROUND_COLOR           0x00000000
+#define defCRTC_PS2                       0x00000000
+#define defCRTC_PS2_VPOS                  0x00000000
+#define defCRTC_PS1_ACTIVE                0x00000000
+#define defCRTC_PS1_NACTIVE               0x00000000
+#define defCRTC_GCLK_EXT                  0x00000000
+#define defCRTC_ALW                       0x00000000
+#define defCRTC_ALW_VPOS                  0x00000000
+#define defCRTC_PSK                       0x00000000
+#define defCRTC_PSK_HPOS                  0x00000000
+#define defCRTC_CV4_START                 0x00000000
+#define defCRTC_CV4_END                   0x00000000
+#define defCRTC_CV4_HPOS                  0x00000000
+#define defCRTC_ECK                       0x00000000
+#define defREFRESH_CNTL                   0x00000000
+#define defGENLCD_CNTL3                   0x000002aa
+#define defGPIO_DATA2                     0x00000000
+#define defGPIO_CNTL3                     0x00000000
+#define defGPIO_CNTL4                     0x00000000
+#define defCHIP_STRAP                     0x00000000
+#define defDISP_DEBUG2                    0x00000000
+#define defDEBUG_BUS_CNTL                 0x00000000
+#define defGAMMA_VALUE1                   0x00000000
+#define defGAMMA_VALUE2                   0x00000000
+#define defGAMMA_SLOPE                    0x00000000
+#define defGEN_STATUS                     0x00000000
+#define defHW_INT                         0x00000000
+#define defDST_OFFSET                     0x00000000
+#define defDST_PITCH                      0x00000000
+#define defDST_PITCH_OFFSET               0x00000000
+#define defDST_X                          0x00000000
+#define defDST_Y                          0x00000000
+#define defDST_X_Y                        0x00000000
+#define defDST_Y_X                        0x00000000
+#define defDST_WIDTH                      0x00000000
+#define defDST_HEIGHT                     0x00000000
+#define defDST_WIDTH_HEIGHT               0x00000000
+#define defDST_HEIGHT_WIDTH               0x00000000
+#define defDST_HEIGHT_WIDTH_8             0x00000000
+#define defDST_HEIGHT_Y                   0x00000000
+#define defDST_WIDTH_X                    0x00000000
+#define defDST_WIDTH_X_INCY               0x00000000
+#define defDST_LINE_START                 0x00000000
+#define defDST_LINE_END                   0x00000000
+#define defBRUSH_OFFSET                   0x00000000
+#define defBRUSH_Y_X                      0x00000000
+#define defDP_BRUSH_FRGD_CLR              0x00000000
+#define defDP_BRUSH_BKGD_CLR              0x00000000
+#define defSRC2_OFFSET                    0x00000000
+#define defSRC2_PITCH                     0x00000000
+#define defSRC2_PITCH_OFFSET              0x00000000
+#define defSRC2_X                         0x00000000
+#define defSRC2_Y                         0x00000000
+#define defSRC2_X_Y                       0x00000000
+#define defSRC2_WIDTH                     0x00000000
+#define defSRC2_HEIGHT                    0x00000000
+#define defSRC2_INC                       0x00000000
+#define defSRC_OFFSET                     0x00000000
+#define defSRC_PITCH                      0x00000000
+#define defSRC_PITCH_OFFSET               0x00000000
+#define defSRC_X                          0x00000000
+#define defSRC_Y                          0x00000000
+#define defSRC_X_Y                        0x00000000
+#define defSRC_Y_X                        0x00000000
+#define defSRC_WIDTH                      0x00000000
+#define defSRC_HEIGHT                     0x00000000
+#define defSRC_INC                        0x00000000
+#define defHOST_DATA0                     0x00000000
+#define defHOST_DATA1                     0x00000000
+#define defHOST_DATA2                     0x00000000
+#define defHOST_DATA3                     0x00000000
+#define defHOST_DATA4                     0x00000000
+#define defHOST_DATA5                     0x00000000
+#define defHOST_DATA6                     0x00000000
+#define defHOST_DATA7                     0x00000000
+#define defHOST_DATA_LAST                 0x00000000
+#define defDP_SRC_FRGD_CLR                0x00000000
+#define defDP_SRC_BKGD_CLR                0x00000000
+#define defSC_LEFT                        0x00000000
+#define defSC_RIGHT                       0x00000000
+#define defSC_TOP                         0x00000000
+#define defSC_BOTTOM                      0x00000000
+#define defSRC_SC_RIGHT                   0x00000000
+#define defSRC_SC_BOTTOM                  0x00000000
+#define defDP_CNTL                        0x00000000
+#define defDP_CNTL_DST_DIR                0x00000000
+#define defDP_DATATYPE                    0x00000000
+#define defDP_MIX                         0x00000000
+#define defDP_WRITE_MSK                   0x00000000
+#define defCLR_CMP_CLR_SRC                0x00000000
+#define defCLR_CMP_CLR_DST                0x00000000
+#define defCLR_CMP_CNTL                   0x00000000
+#define defCLR_CMP_MSK                    0x00000000
+#define defDEFAULT_PITCH_OFFSET           0x00000000
+#define defDEFAULT_SC_BOTTOM_RIGHT        0x00000000
+#define defDEFAULT2_SC_BOTTOM_RIGHT       0x00000000
+#define defREF1_PITCH_OFFSET              0x00000000
+#define defREF2_PITCH_OFFSET              0x00000000
+#define defREF3_PITCH_OFFSET              0x00000000
+#define defREF4_PITCH_OFFSET              0x00000000
+#define defREF5_PITCH_OFFSET              0x00000000
+#define defREF6_PITCH_OFFSET              0x00000000
+#define defDP_GUI_MASTER_CNTL             0x00000000
+#define defSC_TOP_LEFT                    0x00000000
+#define defSC_BOTTOM_RIGHT                0x00000000
+#define defSRC_SC_BOTTOM_RIGHT            0x00000000
+#define defGLOBAL_ALPHA                   0x00000000
+#define defFILTER_COEF                    0x00000000
+#define defMVC_CNTL_START                 0x00000000
+#define defE2_ARITHMETIC_CNTL             0x00000000
+#define defDEBUG0                         0x00000000
+#define defDEBUG1                         0x00000000
+#define defDEBUG2                         0x00000000
+#define defDEBUG3                         0x00000000
+#define defDEBUG4                         0x00000000
+#define defDEBUG5                         0x00000000
+#define defDEBUG6                         0x00000000
+#define defDEBUG7                         0x00000000
+#define defDEBUG8                         0x00000000
+#define defDEBUG9                         0x00000000
+#define defDEBUG10                        0x00000000
+#define defDEBUG11                        0x00000000
+#define defDEBUG12                        0x00000000
+#define defDEBUG13                        0x00000000
+#define defDEBUG14                        0x00000000
+#define defDEBUG15                        0x00000000
+#define defENG_CNTL                       0x00000003
+#define defENG_PERF_CNT                   0x00000000
+#define defIDCT_RUNS                      0x00000000
+#define defIDCT_LEVELS                    0x00000000
+#define defIDCT_CONTROL                   0x00000000
+#define defIDCT_AUTH_CONTROL              0x00000000
+#define defIDCT_AUTH                      0x00000000
+#define defMEM_CNTL                       0x00000006
+#define defMEM_ARB                        0x00000000
+#define defMC_FB_LOCATION                 0x00ff0000
+#define defMEM_EXT_CNTL                   0x00040010
+#define defMC_EXT_MEM_LOCATION            0x07ff0000
+#define defMEM_EXT_TIMING_CNTL            0x00140c73
+#define defMEM_SDRAM_MODE_REG             0x00050000
+#define defMEM_IO_CNTL                    0x00ff00ff
+#define defMC_DEBUG                       0x00000000
+#define defMC_BIST_CTRL                   0x00000000
+#define defMC_BIST_COLLAR_READ            0x00000000
+#define defTC_MISMATCH                    0x00000000
+#define defMC_PERF_MON_CNTL               0x00000000
+#define defMC_PERF_COUNTERS               0x00000000
+#define defWAIT_UNTIL                     0xc5cdcdcd
+#define defISYNC_CNTL                     0x00000000
+#define defRBBM_GUICNTL                   0x00000000
+#define defRBBM_STATUS                    0x81cdcd40
+#define defRBBM_CNTL                      0x0000000f
+#define defRBBM_SOFT_RESET                0x00000000
+#define defNQWAIT_UNTIL                   0x00000001
+#define defRBBM_DEBUG                     0x00000000
+#define defRBBM_CMDFIFO_ADDR              0x0000000d
+#define defRBBM_CMDFIFO_DATAL             0xcdcdcdcd
+#define defRBBM_CMDFIFO_DATAH             0x00000dcd
+#define defRBBM_CMDFIFO_STAT              0x00000d0d
+#define defCLK_PIN_CNTL                   0x0000003f
+#define defPLL_REF_FB_DIV                 0x5a500000
+#define defPLL_CNTL                       0x4b000203
+#define defSCLK_CNTL                      0x00ff0300
+#define defPCLK_CNTL                      0x00010000
+#define defCLK_TEST_CNTL                  0x00000000
+#define defPWRMGT_CNTL                    0x00000004
+#define defPWRMGT_STATUS                  0x00000001
+
+#define CFG_BASE_BOOT_DEFAULT  0x0
+#define CFG_BASE_VALUE         0x0
+#define REG_BASE_BOOT_DEFAULT  0x01
+#define REG_BASE_VALUE         0x10000
+#define MEM_INT_BASE_VALUE     0x100000
+#define MEM_INT_TOP_VALUE_W100 0x15ffff
+#define MEM_EXT_BASE_VALUE     0x800000
+#define MEM_EXT_TOP_VALUE      0x9fffff
+#define WRAP_BUF_BASE_VALUE    0x80000
+#define WRAP_BUF_TOP_VALUE     0xbffff
+
+//----------------------------------------------------------------------------
+// Registers Field Definitions
+
+// DP_GUI_MASTER_CNTL.GMC_Brush_DataType
+// DP_DATATYPE.Brush_DataType
+#define DP_BRUSH_8x8MONOOPA			0   //8x8 mono pattern (expanded to frgd, bkgd)
+#define DP_BRUSH_8x8MONOTRA			1   //8x8 mono pattern (expanded to frgd, leave_alone)
+#define DP_PEN_32x1MONOOPA			6   //32x1 mono pattern (expanded to frgd, bkgd)
+#define DP_PEN_32x1MONOTRA			7   //32x1 mono pattern (expanded to frgd, leave_alone)
+#define DP_BRUSH_8x8COLOR			10  //8x8 color pattern
+#define DP_BRUSH_SOLIDCOLOR			13  //solid color pattern (frgd)
+#define DP_BRUSH_NONE				15	//no brush used
+
+#define SIZE_BRUSH_8x8MONO			2
+#define SIZE_PEN_32x1MONO			1
+#define SIZE_BRUSH_8x8COLOR_8		16
+#define SIZE_BRUSH_8x8COLOR_16		32
+#define MAX_BRUSH_SIZE				SIZE_BRUSH_8x8COLOR_16
+
+// DP_GUI_MASTER_CNTL.GMC_Dst_DataType
+// DP_DATATYPE.Dp_Dst_DataType
+#define DP_DST_8BPP					2   // 8 bpp grey scale
+#define DP_DST_16BPP_1555			3   //16 bpp aRGB 1555
+#define DP_DST_16BPP_444			5   //16 bpp aRGB 4444
+
+// DP_GUI_MASTER_CNTL.GMC_Src_DataType
+// DP_DATATYPE.Dp_Src_DataType
+#define DP_SRC_1BPP_OPA				0   //mono (expanded to frgd, bkgd)
+#define DP_SRC_1BPP_TRA				1   //mono (expanded to frgd, leave_alone)
+#define DP_SRC_COLOR_SAME_AS_DST				3   //color (same as DST)
+#define	DP_SRC_SOLID_COLOR_BLT		4	//solid color for Blt (use frgd)
+#define	DP_SRC_4BPP					5	//4 bpp
+#define	DP_SRC_12BPP_PACKED			6	//12 bpp packed
+
+// DP_GUI_MASTER_CNTL.GMC_Byte_Pix_Order
+// DP_DATATYPE.Dp_Byte_Pix_Order
+#define DP_PIX_ORDER_MSB2LSB		0   //monochrome pixel order from MSBit to LSBit
+#define DP_PIX_ORDER_LSB2MSB		1   //monochrome pixel order from LSBit to MSBit
+
+// DP_GUI_MASTER_CNTL.GMC_Dp_Src_Source
+#define DP_SRC_MEM_LINEAR			1	//loaded from memory (linear trajectory)
+#define DP_SRC_MEM_RECTANGULAR		2   //loaded from memory (rectangular trajectory)
+#define DP_SRC_HOSTDATA_BIT			3   //loaded from hostdata (linear trajectory)
+#define DP_SRC_HOSTDATA_BYTE		4   //loaded from hostdata (linear trajectory & byte-aligned)
+
+// DP_GUI_MASTER_CNTL.GMC_Dp_Op
+#define	DP_OP_ROP					0
+#define	DP_OP_ARITHMETIC			1
+
+// E2_ARITHMETIC_CNTL.opcode
+#define	E2_OPC_GLBALP_ADD_SRC2		0
+#define	E2_OPC_GLBALP_SUB_SRC2		1
+#define	E2_OPC_SRC1_ADD_SRC2		2
+#define	E2_OPC_SRC1_SUB_SRC2		3
+#define	E2_OPC_DST_SADDBLEND_SRC2	4
+#define	E2_OPC_DST_CADDBLEND_SRC2	5
+#define	E2_OPC_DST_CSUBBLEND_SRC2	6
+#define	E2_OPC_LF_SRC2				7
+#define	E2_OPC_SCALE_SRC2			8
+#define	E2_OPC_STRETCH_SRC2			9
+#define	E2_OPC_SRC1_4BPPCPYWEXP		10
+#define	E2_OPC_MC1					11
+#define	E2_OPC_MC2					12
+#define E2_OPC_MC1_IDCT				13
+#define	E2_OPC_MC2_IDCT				14
+#define	E2_OPC_IDCT_ONLY_IFRAME		15
+
+// E2_ARITHMETIC_CNTL.clamp
+#define	E2_CLAMP_OFF				0
+#define	E2_CLAMP_ON					1
+
+// E2_ARITHMETIC_CNTL.rounding
+#define	E2_ROUNDING_TRUNCATE		0
+#define	E2_ROUNDING_TO_INFINITY		1
+
+// E2_ARITHMETIC_CNTL.srcblend
+#define	E2_SRCBLEND_GLOBALALPHA		0
+#define	E2_SRCBLEND_ZERO			1
+#define	E2_SRCBLEND_SRC2ALPHA		2
+#define	E2_SRCBLEND_DSTALPHA		3
+#define	E2_SRCBLEND_ALPHA1PLANE		4
+
+// E2_ARITHMETIC_CNTL.destblend
+#define	E2_DSTBLEND_GLOBALALPHA		0
+#define	E2_DSTBLEND_ZERO			1
+#define	E2_DSTBLEND_SRC2ALPHA		2
+#define	E2_DSTBLEND_DSTALPHA		3
+#define	E2_DSTBLEND_ALPHA1PLANE		4
+
+// LCD_FORMAT.lcd_type
+#define	LCDTYPE_TFT333				0
+#define	LCDTYPE_TFT444				1
+#define	LCDTYPE_TFT555				2
+#define	LCDTYPE_TFT666				3
+#define	LCDTYPE_COLSTNPACK4			4
+#define	LCDTYPE_COLSTNPACK8F1		5
+#define	LCDTYPE_COLSTNPACK8F2		6
+#define	LCDTYPE_COLSTNPACK16		7
+#define	LCDTYPE_MONSTNPACK4			8
+#define	LCDTYPE_MONSTNPACK8			9
+
+// CP_RB_CNTL.rb_bufsz
+#define	RB_SIZE_2K					8
+#define	RB_SIZE_4K					9
+#define	RB_SIZE_8K					10
+#define	RB_SIZE_16K					11
+#define	RB_SIZE_32K					12
+#define	RB_SIZE_64K					13
+
+// GRAPHIC_CTRL.color_depth
+#define	COLOR_DEPTH_1BPP			0
+#define	COLOR_DEPTH_2BPP			1
+#define	COLOR_DEPTH_4BPP			2
+#define	COLOR_DEPTH_8BPP			3
+#define	COLOR_DEPTH_332				4
+#define	COLOR_DEPTH_A444			5
+#define	COLOR_DEPTH_A555			6
+
+// VIDEO_CTRL.video_mode
+#define	VIDEO_MODE_422				0
+#define	VIDEO_MODE_420				1
+
+/* data structure definitions */
+
+typedef struct _chip_id_t {
+     unsigned long vendor_id                      : 16;
+     unsigned long device_id                      : 16;
+     } chip_id_t;
+
+typedef union {
+     unsigned long val : 32;
+     chip_id_t f;
+} chip_id_u;
+
+typedef struct _revision_id_t {
+     unsigned long minor_rev_id                   : 4;
+     unsigned long major_rev_id                   : 4;
+     unsigned long                                : 24;
+     } revision_id_t;
+
+typedef union {
+     unsigned long val : 32;
+     revision_id_t f;
+} revision_id_u;
+
+typedef struct _wrap_buf_a_t {
+     unsigned long offset_addr_a                  : 24;
+     unsigned long block_size_a                   : 3;
+     unsigned long                                : 5;
+     } wrap_buf_a_t;
+
+typedef union {
+     unsigned long val : 32;
+     wrap_buf_a_t f;
+} wrap_buf_a_u;
+
+typedef struct _wrap_buf_b_t {
+     unsigned long offset_addr_b                  : 24;
+     unsigned long block_size_b                   : 3;
+     unsigned long                                : 5;
+     } wrap_buf_b_t;
+
+typedef union {
+     unsigned long val : 32;
+     wrap_buf_b_t f;
+} wrap_buf_b_u;
+
+typedef struct _wrap_top_dir_t {
+     unsigned long top_addr                       : 23;
+     unsigned long                                : 9;
+     } wrap_top_dir_t;
+
+typedef union {
+     unsigned long val : 32;
+     wrap_top_dir_t f;
+} wrap_top_dir_u;
+
+typedef struct _wrap_start_dir_t {
+     unsigned long start_addr                     : 23;
+     unsigned long                                : 9;
+     } wrap_start_dir_t;
+
+typedef union {
+     unsigned long val : 32;
+     wrap_start_dir_t f;
+} wrap_start_dir_u;
+
+typedef struct _cif_cntl_t {
+     unsigned long swap_reg                       : 2;
+     unsigned long swap_fbuf_1                    : 2;
+     unsigned long swap_fbuf_2                    : 2;
+     unsigned long swap_fbuf_3                    : 2;
+     unsigned long pmi_int_disable                : 1;
+     unsigned long pmi_schmen_disable             : 1;
+     unsigned long intb_oe                        : 1;
+     unsigned long en_wait_to_compensate_dq_prop_dly : 1;
+     unsigned long compensate_wait_rd_size        : 2;
+     unsigned long wait_asserted_timeout_val      : 2;
+     unsigned long wait_masked_val                : 2;
+     unsigned long en_wait_timeout                : 1;
+     unsigned long en_one_clk_setup_before_wait   : 1;
+     unsigned long interrupt_active_high          : 1;
+     unsigned long en_overwrite_straps            : 1;
+     unsigned long strap_wait_active_hi           : 1;
+     unsigned long lat_busy_count                 : 2;
+     unsigned long lat_rd_pm4_sclk_busy           : 1;
+     unsigned long dis_system_bits                : 1;
+     unsigned long dis_mr                         : 1;
+     unsigned long cif_spare_1                    : 4;
+     } cif_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     cif_cntl_t f;
+} cif_cntl_u;
+
+typedef struct _cfgreg_base_t {
+     unsigned long cfgreg_base                    : 24;
+     unsigned long                                : 8;
+     } cfgreg_base_t;
+
+typedef union {
+     unsigned long val : 32;
+     cfgreg_base_t f;
+} cfgreg_base_u;
+
+typedef struct _cif_io_t {
+     unsigned long dq_srp                         : 1;
+     unsigned long dq_srn                         : 1;
+     unsigned long dq_sp                          : 4;
+     unsigned long dq_sn                          : 4;
+     unsigned long waitb_srp                      : 1;
+     unsigned long waitb_srn                      : 1;
+     unsigned long waitb_sp                       : 4;
+     unsigned long waitb_sn                       : 4;
+     unsigned long intb_srp                       : 1;
+     unsigned long intb_srn                       : 1;
+     unsigned long intb_sp                        : 4;
+     unsigned long intb_sn                        : 4;
+     unsigned long                                : 2;
+     } cif_io_t;
+
+typedef union {
+     unsigned long val : 32;
+     cif_io_t f;
+} cif_io_u;
+
+typedef struct _cif_read_dbg_t {
+     unsigned long unpacker_pre_fetch_trig_gen    : 2;
+     unsigned long dly_second_rd_fetch_trig       : 1;
+     unsigned long rst_rd_burst_id                : 1;
+     unsigned long dis_rd_burst_id                : 1;
+     unsigned long en_block_rd_when_packer_is_not_emp : 1;
+     unsigned long dis_pre_fetch_cntl_sm          : 1;
+     unsigned long rbbm_chrncy_dis                : 1;
+     unsigned long rbbm_rd_after_wr_lat           : 2;
+     unsigned long dis_be_during_rd               : 1;
+     unsigned long one_clk_invalidate_pulse       : 1;
+     unsigned long dis_chnl_priority              : 1;
+     unsigned long rst_read_path_a_pls            : 1;
+     unsigned long rst_read_path_b_pls            : 1;
+     unsigned long dis_reg_rd_fetch_trig          : 1;
+     unsigned long dis_rd_fetch_trig_from_ind_addr : 1;
+     unsigned long dis_rd_same_byte_to_trig_fetch : 1;
+     unsigned long dis_dir_wrap                   : 1;
+     unsigned long dis_ring_buf_to_force_dec      : 1;
+     unsigned long dis_addr_comp_in_16bit         : 1;
+     unsigned long clr_w                          : 1;
+     unsigned long err_rd_tag_is_3                : 1;
+     unsigned long err_load_when_ful_a            : 1;
+     unsigned long err_load_when_ful_b            : 1;
+     unsigned long                                : 7;
+     } cif_read_dbg_t;
+
+typedef union {
+     unsigned long val : 32;
+     cif_read_dbg_t f;
+} cif_read_dbg_u;
+
+typedef struct _cif_write_dbg_t {
+     unsigned long packer_timeout_count           : 2;
+     unsigned long en_upper_load_cond             : 1;
+     unsigned long en_chnl_change_cond            : 1;
+     unsigned long dis_addr_comp_cond             : 1;
+     unsigned long dis_load_same_byte_addr_cond   : 1;
+     unsigned long dis_timeout_cond               : 1;
+     unsigned long dis_timeout_during_rbbm        : 1;
+     unsigned long dis_packer_ful_during_rbbm_timeout : 1;
+     unsigned long en_dword_split_to_rbbm         : 1;
+     unsigned long en_dummy_val                   : 1;
+     unsigned long dummy_val_sel                  : 1;
+     unsigned long mask_pm4_wrptr_dec             : 1;
+     unsigned long dis_mc_clean_cond              : 1;
+     unsigned long err_two_reqi_during_ful        : 1;
+     unsigned long err_reqi_during_idle_clk       : 1;
+     unsigned long err_global                     : 1;
+     unsigned long en_wr_buf_dbg_load             : 1;
+     unsigned long en_wr_buf_dbg_path             : 1;
+     unsigned long sel_wr_buf_byte                : 3;
+     unsigned long dis_rd_flush_wr                : 1;
+     unsigned long dis_packer_ful_cond            : 1;
+     unsigned long dis_invalidate_by_ops_chnl     : 1;
+     unsigned long en_halt_when_reqi_err          : 1;
+     unsigned long cif_spare_2                    : 5;
+     unsigned long                                : 1;
+     } cif_write_dbg_t;
+
+typedef union {
+     unsigned long val : 32;
+     cif_write_dbg_t f;
+} cif_write_dbg_u;
+
+typedef struct _ind_addr_a_0_t {
+     unsigned char ind_addr_a_0                   : 8;
+     } ind_addr_a_0_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_addr_a_0_t f;
+} ind_addr_a_0_u;
+
+typedef struct _ind_addr_a_1_t {
+     unsigned char ind_addr_a_1                   : 8;
+     } ind_addr_a_1_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_addr_a_1_t f;
+} ind_addr_a_1_u;
+
+typedef struct _ind_addr_a_2_t {
+     unsigned char ind_addr_a_2                   : 8;
+     } ind_addr_a_2_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_addr_a_2_t f;
+} ind_addr_a_2_u;
+
+typedef struct _ind_data_a_t {
+     unsigned char ind_data_a                     : 8;
+     } ind_data_a_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_data_a_t f;
+} ind_data_a_u;
+
+typedef struct _reg_base_t {
+     unsigned char reg_base                       : 8;
+     } reg_base_t;
+
+typedef union {
+     unsigned char val : 8;
+     reg_base_t f;
+} reg_base_u;
+
+typedef struct _intf_cntl_t {
+     unsigned char ad_inc_a                       : 1;
+     unsigned char ring_buf_a                     : 1;
+     unsigned char rd_fetch_trigger_a             : 1;
+     unsigned char rd_data_rdy_a                  : 1;
+     unsigned char ad_inc_b                       : 1;
+     unsigned char ring_buf_b                     : 1;
+     unsigned char rd_fetch_trigger_b             : 1;
+     unsigned char rd_data_rdy_b                  : 1;
+     } intf_cntl_t;
+
+typedef union {
+     unsigned char val : 8;
+     intf_cntl_t f;
+} intf_cntl_u;
+
+typedef struct _status_t {
+     unsigned char wr_fifo_available_space        : 2;
+     unsigned char fbuf_wr_pipe_emp               : 1;
+     unsigned char soft_reset                     : 1;
+     unsigned char system_pwm_mode                : 2;
+     unsigned char mem_access_dis                 : 1;
+     unsigned char en_pre_fetch                   : 1;
+     } status_t;
+
+typedef union {
+     unsigned char val : 8;
+     status_t f;
+} status_u;
+
+typedef struct _cpu_defaults_t {
+     unsigned char unpack_rd_data                 : 1;
+     unsigned char access_ind_addr_a              : 1;
+     unsigned char access_ind_addr_b              : 1;
+     unsigned char access_scratch_reg             : 1;
+     unsigned char pack_wr_data                   : 1;
+     unsigned char transition_size                : 1;
+     unsigned char en_read_buf_mode               : 1;
+     unsigned char rd_fetch_scratch               : 1;
+     } cpu_defaults_t;
+
+typedef union {
+     unsigned char val : 8;
+     cpu_defaults_t f;
+} cpu_defaults_u;
+
+typedef struct _ind_addr_b_0_t {
+     unsigned char ind_addr_b_0                   : 8;
+     } ind_addr_b_0_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_addr_b_0_t f;
+} ind_addr_b_0_u;
+
+typedef struct _ind_addr_b_1_t {
+     unsigned char ind_addr_b_1                   : 8;
+     } ind_addr_b_1_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_addr_b_1_t f;
+} ind_addr_b_1_u;
+
+typedef struct _ind_addr_b_2_t {
+     unsigned char ind_addr_b_2                   : 8;
+     } ind_addr_b_2_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_addr_b_2_t f;
+} ind_addr_b_2_u;
+
+typedef struct _ind_data_b_t {
+     unsigned char ind_data_b                     : 8;
+     } ind_data_b_t;
+
+typedef union {
+     unsigned char val : 8;
+     ind_data_b_t f;
+} ind_data_b_u;
+
+typedef struct _pm4_rptr_t {
+     unsigned char pm4_rptr                       : 8;
+     } pm4_rptr_t;
+
+typedef union {
+     unsigned char val : 8;
+     pm4_rptr_t f;
+} pm4_rptr_u;
+
+typedef struct _scratch_t {
+     unsigned char scratch                        : 8;
+     } scratch_t;
+
+typedef union {
+     unsigned char val : 8;
+     scratch_t f;
+} scratch_u;
+
+typedef struct _pm4_wrptr_0_t {
+     unsigned char pm4_wrptr_0                    : 8;
+     } pm4_wrptr_0_t;
+
+typedef union {
+     unsigned char val : 8;
+     pm4_wrptr_0_t f;
+} pm4_wrptr_0_u;
+
+typedef struct _pm4_wrptr_1_t {
+     unsigned char pm4_wrptr_1                    : 6;
+     unsigned char rd_fetch_pm4_rptr              : 1;
+     unsigned char wrptr_atomic_update_w          : 1;
+     } pm4_wrptr_1_t;
+
+typedef union {
+     unsigned char val : 8;
+     pm4_wrptr_1_t f;
+} pm4_wrptr_1_u;
+
+typedef struct _cp_rb_cntl_t {
+     unsigned long rb_bufsz                       : 6;
+     unsigned long                                : 2;
+     unsigned long rb_blksz                       : 6;
+     unsigned long                                : 2;
+     unsigned long buf_swap                       : 2;
+     unsigned long max_fetch                      : 2;
+     unsigned long                                : 7;
+     unsigned long rb_no_update                   : 1;
+     unsigned long                                : 3;
+     unsigned long rb_rptr_wr_ena                 : 1;
+     } cp_rb_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+typedef struct _cp_rb_base_t {
+     unsigned long                                : 2;
+     unsigned long rb_base                        : 22;
+     unsigned long                                : 8;
+     } cp_rb_base_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+typedef struct _cp_rb_rptr_addr_t {
+     unsigned long rb_rptr_swap                   : 2;
+     unsigned long rb_rptr_addr                   : 22;
+     unsigned long                                : 8;
+     } cp_rb_rptr_addr_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+typedef struct _cp_rb_rptr_t {
+     unsigned long rb_rptr                        : 23;
+     unsigned long                                : 9;
+     } cp_rb_rptr_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+typedef struct _cp_rb_rptr_wr_t {
+     unsigned long rb_rptr_wr                     : 23;
+     unsigned long                                : 9;
+     } cp_rb_rptr_wr_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+typedef struct _cp_rb_wptr_t {
+     unsigned long rb_wptr                        : 23;
+     unsigned long                                : 9;
+     } cp_rb_wptr_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+typedef struct _cp_ib_base_t {
+     unsigned long                                : 2;
+     unsigned long ib_base                        : 22;
+     unsigned long                                : 8;
+     } cp_ib_base_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_ib_base_t f;
+} cp_ib_base_u;
+
+typedef struct _cp_ib_bufsz_t {
+     unsigned long ib_bufsz                       : 23;
+     unsigned long                                : 9;
+     } cp_ib_bufsz_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_ib_bufsz_t f;
+} cp_ib_bufsz_u;
+
+typedef struct _cp_csq_cntl_t {
+     unsigned long csq_cnt_primary                : 8;
+     unsigned long csq_cnt_indirect               : 8;
+     unsigned long                                : 12;
+     unsigned long csq_mode                       : 4;
+     } cp_csq_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_csq_cntl_t f;
+} cp_csq_cntl_u;
+
+typedef struct _cp_csq_aper_primary_t {
+     unsigned long cp_csq_aper_primary            : 32;
+     } cp_csq_aper_primary_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_csq_aper_primary_t f;
+} cp_csq_aper_primary_u;
+
+typedef struct _cp_csq_aper_indirect_t {
+     unsigned long cp_csq_aper_indirect           : 32;
+     } cp_csq_aper_indirect_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_csq_aper_indirect_t f;
+} cp_csq_aper_indirect_u;
+
+typedef struct _cp_me_cntl_t {
+     unsigned long me_stat                        : 16;
+     unsigned long me_statmux                     : 5;
+     unsigned long                                : 8;
+     unsigned long me_busy                        : 1;
+     unsigned long me_mode                        : 1;
+     unsigned long me_step                        : 1;
+     } cp_me_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+typedef struct _cp_me_ram_addr_t {
+     unsigned long me_ram_addr                    : 8;
+     unsigned long                                : 24;
+     } cp_me_ram_addr_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_me_ram_addr_t f;
+} cp_me_ram_addr_u;
+
+typedef struct _cp_me_ram_raddr_t {
+     unsigned long me_ram_raddr                   : 8;
+     unsigned long                                : 24;
+     } cp_me_ram_raddr_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+typedef struct _cp_me_ram_datah_t {
+     unsigned long me_ram_datah                   : 6;
+     unsigned long                                : 26;
+     } cp_me_ram_datah_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_me_ram_datah_t f;
+} cp_me_ram_datah_u;
+
+typedef struct _cp_me_ram_datal_t {
+     unsigned long me_ram_datal                   : 32;
+     } cp_me_ram_datal_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_me_ram_datal_t f;
+} cp_me_ram_datal_u;
+
+typedef struct _cp_debug_t {
+     unsigned long cp_debug                       : 32;
+     } cp_debug_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+typedef struct _scratch_reg0_t {
+     unsigned long scratch_reg0                   : 32;
+     } scratch_reg0_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+typedef struct _scratch_reg1_t {
+     unsigned long scratch_reg1                   : 32;
+     } scratch_reg1_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+typedef struct _scratch_reg2_t {
+     unsigned long scratch_reg2                   : 32;
+     } scratch_reg2_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+typedef struct _scratch_reg3_t {
+     unsigned long scratch_reg3                   : 32;
+     } scratch_reg3_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+typedef struct _scratch_reg4_t {
+     unsigned long scratch_reg4                   : 32;
+     } scratch_reg4_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+typedef struct _scratch_reg5_t {
+     unsigned long scratch_reg5                   : 32;
+     } scratch_reg5_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+typedef struct _scratch_umsk_t {
+     unsigned long scratch_umsk                   : 6;
+     unsigned long                                : 10;
+     unsigned long scratch_swap                   : 2;
+     unsigned long                                : 14;
+     } scratch_umsk_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+typedef struct _scratch_addr_t {
+     unsigned long                                : 5;
+     unsigned long scratch_addr                   : 27;
+     } scratch_addr_t;
+
+typedef union {
+     unsigned long val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+typedef struct _cp_csq_addr_t {
+     unsigned long                                : 2;
+     unsigned long csq_addr                       : 8;
+     unsigned long                                : 22;
+     } cp_csq_addr_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_csq_addr_t f;
+} cp_csq_addr_u;
+
+typedef struct _cp_csq_data_t {
+     unsigned long csq_data                       : 32;
+     } cp_csq_data_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_csq_data_t f;
+} cp_csq_data_u;
+
+typedef struct _cp_csq_stat_t {
+     unsigned long csq_rptr_primary               : 8;
+     unsigned long csq_wptr_primary               : 8;
+     unsigned long csq_rptr_indirect              : 8;
+     unsigned long csq_wptr_indirect              : 8;
+     } cp_csq_stat_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_csq_stat_t f;
+} cp_csq_stat_u;
+
+typedef struct _cp_stat_t {
+     unsigned long mru_busy                       : 1;
+     unsigned long mwu_busy                       : 1;
+     unsigned long rsiu_busy                      : 1;
+     unsigned long rciu_busy                      : 1;
+     unsigned long                                : 5;
+     unsigned long csf_primary_busy               : 1;
+     unsigned long csf_indirect_busy              : 1;
+     unsigned long csq_primary_busy               : 1;
+     unsigned long csq_indirect_busy              : 1;
+     unsigned long csi_busy                       : 1;
+     unsigned long                                : 14;
+     unsigned long guidma_busy                    : 1;
+     unsigned long viddma_busy                    : 1;
+     unsigned long cmdstrm_busy                   : 1;
+     unsigned long cp_busy                        : 1;
+     } cp_stat_t;
+
+typedef union {
+     unsigned long val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+typedef struct _gen_int_cntl_t {
+     unsigned long crtc_vblank_mask               : 1;
+     unsigned long crtc_vline_mask                : 1;
+     unsigned long crtc_hwint1_mask               : 1;
+     unsigned long crtc_hwint2_mask               : 1;
+     unsigned long                                : 15;
+     unsigned long gui_idle_mask                  : 1;
+     unsigned long                                : 8;
+     unsigned long pm4_idle_int_mask              : 1;
+     unsigned long dvi_i2c_int_mask               : 1;
+     unsigned long                                : 2;
+     } gen_int_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     gen_int_cntl_t f;
+} gen_int_cntl_u;
+
+typedef struct _gen_int_status_rd_t {
+     unsigned long crtc_vblank_stat               : 1;
+     unsigned long crtc_vline_stat                : 1;
+     unsigned long crtc_hwint1_stat               : 1;
+     unsigned long crtc_hwint2_stat               : 1;
+     unsigned long                                : 15;
+     unsigned long gui_idle_stat                  : 1;
+     unsigned long                                : 8;
+     unsigned long pm4_idle_int_stat              : 1;
+     unsigned long dvi_i2c_int_stat               : 1;
+     unsigned long                                : 2;
+     } gen_int_status_rd_t;
+
+typedef union {
+     unsigned long val : 32;
+     gen_int_status_rd_t f;
+} gen_int_status_rd_u;
+
+typedef struct _gen_int_status_wr_t {
+     unsigned long crtc_vblank_stat_ak            : 1;
+     unsigned long crtc_vline_stat_ak             : 1;
+     unsigned long crtc_hwint1_stat_ak            : 1;
+     unsigned long crtc_hwint2_stat_ak            : 1;
+     unsigned long                                : 15;
+     unsigned long gui_idle_stat_ak               : 1;
+     unsigned long                                : 8;
+     unsigned long pm4_idle_int_ak                : 1;
+     unsigned long dvi_i2c_int_ak                 : 1;
+     unsigned long                                : 2;
+     } gen_int_status_wr_t;
+
+typedef union {
+     unsigned long val : 32;
+     gen_int_status_wr_t f;
+} gen_int_status_wr_u;
+
+typedef struct _lcd_format_t {
+     unsigned long lcd_type                       : 4;
+     unsigned long color_to_mono                  : 1;
+     unsigned long data_inv                       : 1;
+     unsigned long stn_fm                         : 2;
+     unsigned long tft_fm                         : 2;
+     unsigned long scan_lr_en                     : 1;
+     unsigned long scan_ud_en                     : 1;
+     unsigned long pol_inv                        : 1;
+     unsigned long rst_fm                         : 1;
+     unsigned long yuv_to_rgb                     : 1;
+     unsigned long hr_tft                         : 1;
+     unsigned long ulc_panel                      : 1;
+     unsigned long                                : 15;
+     } lcd_format_t;
+
+typedef union {
+     unsigned long val : 32;
+     lcd_format_t f;
+} lcd_format_u;
+
+typedef struct _graphic_ctrl_t {
+     unsigned long color_depth                    : 3;
+     unsigned long portrait_mode                  : 2;
+     unsigned long low_power_on                   : 1;
+     unsigned long req_freq                       : 4;
+     unsigned long en_crtc                        : 1;
+     unsigned long en_graphic_req                 : 1;
+     unsigned long en_graphic_crtc                : 1;
+     unsigned long total_req_graphic              : 9;
+     unsigned long lcd_pclk_on                    : 1;
+     unsigned long lcd_sclk_on                    : 1;
+     unsigned long pclk_running                   : 1;
+     unsigned long sclk_running                   : 1;
+     unsigned long                                : 6;
+     } graphic_ctrl_t;
+
+typedef union {
+     unsigned long val : 32;
+     graphic_ctrl_t f;
+} graphic_ctrl_u;
+
+typedef struct _graphic_offset_t {
+     unsigned long graphic_offset                 : 24;
+     unsigned long                                : 8;
+     } graphic_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     graphic_offset_t f;
+} graphic_offset_u;
+
+typedef struct _graphic_pitch_t {
+     unsigned long graphic_pitch                  : 11;
+     unsigned long                                : 21;
+     } graphic_pitch_t;
+
+typedef union {
+     unsigned long val : 32;
+     graphic_pitch_t f;
+} graphic_pitch_u;
+
+typedef struct _crtc_total_t {
+     unsigned long crtc_h_total                   : 10;
+     unsigned long                                : 6;
+     unsigned long crtc_v_total                   : 10;
+     unsigned long                                : 6;
+     } crtc_total_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_total_t f;
+} crtc_total_u;
+
+typedef struct _active_h_disp_t {
+     unsigned long active_h_start                 : 10;
+     unsigned long                                : 6;
+     unsigned long active_h_end                   : 10;
+     unsigned long                                : 6;
+     } active_h_disp_t;
+
+typedef union {
+     unsigned long val : 32;
+     active_h_disp_t f;
+} active_h_disp_u;
+
+typedef struct _active_v_disp_t {
+     unsigned long active_v_start                 : 10;
+     unsigned long                                : 6;
+     unsigned long active_v_end                   : 10;
+     unsigned long                                : 6;
+     } active_v_disp_t;
+
+typedef union {
+     unsigned long val : 32;
+     active_v_disp_t f;
+} active_v_disp_u;
+
+typedef struct _graphic_h_disp_t {
+     unsigned long graphic_h_start                : 10;
+     unsigned long                                : 6;
+     unsigned long graphic_h_end                  : 10;
+     unsigned long                                : 6;
+     } graphic_h_disp_t;
+
+typedef union {
+     unsigned long val : 32;
+     graphic_h_disp_t f;
+} graphic_h_disp_u;
+
+typedef struct _graphic_v_disp_t {
+     unsigned long graphic_v_start                : 10;
+     unsigned long                                : 6;
+     unsigned long graphic_v_end                  : 10;
+     unsigned long                                : 6;
+     } graphic_v_disp_t;
+
+typedef union {
+     unsigned long val : 32;
+     graphic_v_disp_t f;
+} graphic_v_disp_u;
+
+typedef struct _video_ctrl_t {
+     unsigned long video_mode                     : 1;
+     unsigned long keyer_en                       : 1;
+     unsigned long en_video_req                   : 1;
+     unsigned long en_graphic_req_video           : 1;
+     unsigned long en_video_crtc                  : 1;
+     unsigned long video_hor_exp                  : 2;
+     unsigned long video_ver_exp                  : 2;
+     unsigned long uv_combine                     : 1;
+     unsigned long total_req_video                : 9;
+     unsigned long video_ch_sel                   : 1;
+     unsigned long video_portrait                 : 2;
+     unsigned long yuv2rgb_en                     : 1;
+     unsigned long yuv2rgb_option                 : 1;
+     unsigned long video_inv_hor                  : 1;
+     unsigned long video_inv_ver                  : 1;
+     unsigned long gamma_sel                      : 2;
+     unsigned long dis_limit                      : 1;
+     unsigned long en_uv_hblend                   : 1;
+     unsigned long rgb_gamma_sel                  : 2;
+     } video_ctrl_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_ctrl_t f;
+} video_ctrl_u;
+
+typedef struct _graphic_key_t {
+     unsigned long keyer_color                    : 16;
+     unsigned long keyer_mask                     : 16;
+     } graphic_key_t;
+
+typedef union {
+     unsigned long val : 32;
+     graphic_key_t f;
+} graphic_key_u;
+
+typedef struct _video_y_offset_t {
+     unsigned long y_offset                       : 24;
+     unsigned long                                : 8;
+     } video_y_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_y_offset_t f;
+} video_y_offset_u;
+
+typedef struct _video_y_pitch_t {
+     unsigned long y_pitch                        : 11;
+     unsigned long                                : 21;
+     } video_y_pitch_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_y_pitch_t f;
+} video_y_pitch_u;
+
+typedef struct _video_u_offset_t {
+     unsigned long u_offset                       : 24;
+     unsigned long                                : 8;
+     } video_u_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_u_offset_t f;
+} video_u_offset_u;
+
+typedef struct _video_u_pitch_t {
+     unsigned long u_pitch                        : 11;
+     unsigned long                                : 21;
+     } video_u_pitch_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_u_pitch_t f;
+} video_u_pitch_u;
+
+typedef struct _video_v_offset_t {
+     unsigned long v_offset                       : 24;
+     unsigned long                                : 8;
+     } video_v_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_v_offset_t f;
+} video_v_offset_u;
+
+typedef struct _video_v_pitch_t {
+     unsigned long v_pitch                        : 11;
+     unsigned long                                : 21;
+     } video_v_pitch_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_v_pitch_t f;
+} video_v_pitch_u;
+
+typedef struct _video_h_pos_t {
+     unsigned long video_h_start                  : 10;
+     unsigned long                                : 6;
+     unsigned long video_h_end                    : 10;
+     unsigned long                                : 6;
+     } video_h_pos_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_h_pos_t f;
+} video_h_pos_u;
+
+typedef struct _video_v_pos_t {
+     unsigned long video_v_start                  : 10;
+     unsigned long                                : 6;
+     unsigned long video_v_end                    : 10;
+     unsigned long                                : 6;
+     } video_v_pos_t;
+
+typedef union {
+     unsigned long val : 32;
+     video_v_pos_t f;
+} video_v_pos_u;
+
+typedef struct _brightness_cntl_t {
+     unsigned long brightness                     : 7;
+     unsigned long                                : 25;
+     } brightness_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     brightness_cntl_t f;
+} brightness_cntl_u;
+
+typedef struct _cursor1_offset_t {
+     unsigned long cur1_offset                    : 24;
+     unsigned long cur1_x_offset                  : 4;
+     unsigned long cur1_y_offset                  : 4;
+     } cursor1_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor1_offset_t f;
+} cursor1_offset_u;
+
+typedef struct _cursor1_h_pos_t {
+     unsigned long cur1_h_start                   : 10;
+     unsigned long                                : 6;
+     unsigned long cur1_h_end                     : 10;
+     unsigned long                                : 5;
+     unsigned long cur1_en                        : 1;
+     } cursor1_h_pos_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor1_h_pos_t f;
+} cursor1_h_pos_u;
+
+typedef struct _cursor1_v_pos_t {
+     unsigned long cur1_v_start                   : 10;
+     unsigned long                                : 6;
+     unsigned long cur1_v_end                     : 10;
+     unsigned long                                : 6;
+     } cursor1_v_pos_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor1_v_pos_t f;
+} cursor1_v_pos_u;
+
+typedef struct _cursor1_color0_t {
+     unsigned long cur1_color0_r                  : 8;
+     unsigned long cur1_color0_g                  : 8;
+     unsigned long cur1_color0_b                  : 8;
+     unsigned long                                : 8;
+     } cursor1_color0_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor1_color0_t f;
+} cursor1_color0_u;
+
+typedef struct _cursor1_color1_t {
+     unsigned long cur1_color1_r                  : 8;
+     unsigned long cur1_color1_g                  : 8;
+     unsigned long cur1_color1_b                  : 8;
+     unsigned long                                : 8;
+     } cursor1_color1_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor1_color1_t f;
+} cursor1_color1_u;
+
+typedef struct _cursor2_offset_t {
+     unsigned long cur2_offset                    : 24;
+     unsigned long cur2_x_offset                  : 4;
+     unsigned long cur2_y_offset                  : 4;
+     } cursor2_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor2_offset_t f;
+} cursor2_offset_u;
+
+typedef struct _cursor2_h_pos_t {
+     unsigned long cur2_h_start                   : 10;
+     unsigned long                                : 6;
+     unsigned long cur2_h_end                     : 10;
+     unsigned long                                : 5;
+     unsigned long cur2_en                        : 1;
+     } cursor2_h_pos_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor2_h_pos_t f;
+} cursor2_h_pos_u;
+
+typedef struct _cursor2_v_pos_t {
+     unsigned long cur2_v_start                   : 10;
+     unsigned long                                : 6;
+     unsigned long cur2_v_end                     : 10;
+     unsigned long                                : 6;
+     } cursor2_v_pos_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor2_v_pos_t f;
+} cursor2_v_pos_u;
+
+typedef struct _cursor2_color0_t {
+     unsigned long cur2_color0_r                  : 8;
+     unsigned long cur2_color0_g                  : 8;
+     unsigned long cur2_color0_b                  : 8;
+     unsigned long                                : 8;
+     } cursor2_color0_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor2_color0_t f;
+} cursor2_color0_u;
+
+typedef struct _cursor2_color1_t {
+     unsigned long cur2_color1_r                  : 8;
+     unsigned long cur2_color1_g                  : 8;
+     unsigned long cur2_color1_b                  : 8;
+     unsigned long                                : 8;
+     } cursor2_color1_t;
+
+typedef union {
+     unsigned long val : 32;
+     cursor2_color1_t f;
+} cursor2_color1_u;
+
+typedef struct _disp_int_cntl_t {
+     unsigned long vline_int_pos                  : 10;
+     unsigned long                                : 6;
+     unsigned long hpos_int_pos                   : 10;
+     unsigned long                                : 4;
+     unsigned long vblank_int_pol                 : 1;
+     unsigned long frame_int_pol                  : 1;
+     } disp_int_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     disp_int_cntl_t f;
+} disp_int_cntl_u;
+
+typedef struct _crtc_ss_t {
+     unsigned long ss_start                       : 10;
+     unsigned long                                : 6;
+     unsigned long ss_end                         : 10;
+     unsigned long                                : 2;
+     unsigned long ss_align                       : 1;
+     unsigned long ss_pol                         : 1;
+     unsigned long ss_run_mode                    : 1;
+     unsigned long ss_en                          : 1;
+     } crtc_ss_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_ss_t f;
+} crtc_ss_u;
+
+typedef struct _crtc_ls_t {
+     unsigned long ls_start                       : 10;
+     unsigned long                                : 6;
+     unsigned long ls_end                         : 10;
+     unsigned long                                : 2;
+     unsigned long ls_align                       : 1;
+     unsigned long ls_pol                         : 1;
+     unsigned long ls_run_mode                    : 1;
+     unsigned long ls_en                          : 1;
+     } crtc_ls_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_ls_t f;
+} crtc_ls_u;
+
+typedef struct _crtc_rev_t {
+     unsigned long rev_pos                        : 10;
+     unsigned long                                : 6;
+     unsigned long rev_align                      : 1;
+     unsigned long rev_freq_nref                  : 5;
+     unsigned long rev_en                         : 1;
+     unsigned long                                : 9;
+     } crtc_rev_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_rev_t f;
+} crtc_rev_u;
+
+typedef struct _crtc_dclk_t {
+     unsigned long dclk_start                     : 10;
+     unsigned long                                : 6;
+     unsigned long dclk_end                       : 10;
+     unsigned long                                : 1;
+     unsigned long dclk_run_mode                  : 2;
+     unsigned long dclk_pol                       : 1;
+     unsigned long dclk_align                     : 1;
+     unsigned long dclk_en                        : 1;
+     } crtc_dclk_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_dclk_t f;
+} crtc_dclk_u;
+
+typedef struct _crtc_gs_t {
+     unsigned long gs_start                       : 10;
+     unsigned long                                : 6;
+     unsigned long gs_end                         : 10;
+     unsigned long                                : 3;
+     unsigned long gs_align                       : 1;
+     unsigned long gs_pol                         : 1;
+     unsigned long gs_en                          : 1;
+     } crtc_gs_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_gs_t f;
+} crtc_gs_u;
+
+typedef struct _crtc_vpos_gs_t {
+     unsigned long gs_vpos_start                  : 10;
+     unsigned long                                : 6;
+     unsigned long gs_vpos_end                    : 10;
+     unsigned long                                : 6;
+     } crtc_vpos_gs_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_vpos_gs_t f;
+} crtc_vpos_gs_u;
+
+typedef struct _crtc_gclk_t {
+     unsigned long gclk_start                     : 10;
+     unsigned long                                : 6;
+     unsigned long gclk_end                       : 10;
+     unsigned long                                : 3;
+     unsigned long gclk_align                     : 1;
+     unsigned long gclk_pol                       : 1;
+     unsigned long gclk_en                        : 1;
+     } crtc_gclk_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_gclk_t f;
+} crtc_gclk_u;
+
+typedef struct _crtc_goe_t {
+     unsigned long goe_start                      : 10;
+     unsigned long                                : 6;
+     unsigned long goe_end                        : 10;
+     unsigned long                                : 3;
+     unsigned long goe_align                      : 1;
+     unsigned long goe_pol                        : 1;
+     unsigned long goe_en                         : 1;
+     } crtc_goe_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_goe_t f;
+} crtc_goe_u;
+
+typedef struct _crtc_frame_t {
+     unsigned long crtc_fr_start                  : 10;
+     unsigned long                                : 6;
+     unsigned long crtc_fr_end                    : 10;
+     unsigned long                                : 4;
+     unsigned long crtc_frame_en                  : 1;
+     unsigned long crtc_frame_align               : 1;
+     } crtc_frame_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_frame_t f;
+} crtc_frame_u;
+
+typedef struct _crtc_frame_vpos_t {
+     unsigned long crtc_fr_vpos                   : 10;
+     unsigned long                                : 22;
+     } crtc_frame_vpos_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_frame_vpos_t f;
+} crtc_frame_vpos_u;
+
+typedef struct _gpio_data_t {
+     unsigned long gio_out                        : 16;
+     unsigned long gio_in                         : 16;
+     } gpio_data_t;
+
+typedef union {
+     unsigned long val : 32;
+     gpio_data_t f;
+} gpio_data_u;
+
+typedef struct _gpio_cntl1_t {
+     unsigned long gio_pd                         : 16;
+     unsigned long gio_schmen                     : 16;
+     } gpio_cntl1_t;
+
+typedef union {
+     unsigned long val : 32;
+     gpio_cntl1_t f;
+} gpio_cntl1_u;
+
+typedef struct _gpio_cntl2_t {
+     unsigned long gio_oe                         : 16;
+     unsigned long gio_srp                        : 1;
+     unsigned long gio_srn                        : 1;
+     unsigned long gio_sp                         : 4;
+     unsigned long gio_sn                         : 4;
+     unsigned long                                : 6;
+     } gpio_cntl2_t;
+
+typedef union {
+     unsigned long val : 32;
+     gpio_cntl2_t f;
+} gpio_cntl2_u;
+
+typedef struct _lcdd_cntl1_t {
+     unsigned long lcdd_pd                        : 18;
+     unsigned long lcdd_srp                       : 1;
+     unsigned long lcdd_srn                       : 1;
+     unsigned long lcdd_sp                        : 4;
+     unsigned long lcdd_sn                        : 4;
+     unsigned long lcdd_align                     : 1;
+     unsigned long                                : 3;
+     } lcdd_cntl1_t;
+
+typedef union {
+     unsigned long val : 32;
+     lcdd_cntl1_t f;
+} lcdd_cntl1_u;
+
+typedef struct _lcdd_cntl2_t {
+     unsigned long lcdd_oe                        : 18;
+     unsigned long                                : 14;
+     } lcdd_cntl2_t;
+
+typedef union {
+     unsigned long val : 32;
+     lcdd_cntl2_t f;
+} lcdd_cntl2_u;
+
+typedef struct _genlcd_cntl1_t {
+     unsigned long dclk_oe                        : 1;
+     unsigned long dclk_pd                        : 1;
+     unsigned long dclk_srp                       : 1;
+     unsigned long dclk_srn                       : 1;
+     unsigned long dclk_sp                        : 4;
+     unsigned long dclk_sn                        : 4;
+     unsigned long ss_oe                          : 1;
+     unsigned long ss_pd                          : 1;
+     unsigned long ls_oe                          : 1;
+     unsigned long ls_pd                          : 1;
+     unsigned long gs_oe                          : 1;
+     unsigned long gs_pd                          : 1;
+     unsigned long goe_oe                         : 1;
+     unsigned long goe_pd                         : 1;
+     unsigned long rev_oe                         : 1;
+     unsigned long rev_pd                         : 1;
+     unsigned long frame_oe                       : 1;
+     unsigned long frame_pd                       : 1;
+     unsigned long                                : 8;
+     } genlcd_cntl1_t;
+
+typedef union {
+     unsigned long val : 32;
+     genlcd_cntl1_t f;
+} genlcd_cntl1_u;
+
+typedef struct _genlcd_cntl2_t {
+     unsigned long gclk_oe                        : 1;
+     unsigned long gclk_pd                        : 1;
+     unsigned long gclk_srp                       : 1;
+     unsigned long gclk_srn                       : 1;
+     unsigned long gclk_sp                        : 4;
+     unsigned long gclk_sn                        : 4;
+     unsigned long genlcd_srp                     : 1;
+     unsigned long genlcd_srn                     : 1;
+     unsigned long genlcd_sp                      : 4;
+     unsigned long genlcd_sn                      : 4;
+     unsigned long                                : 10;
+     } genlcd_cntl2_t;
+
+typedef union {
+     unsigned long val : 32;
+     genlcd_cntl2_t f;
+} genlcd_cntl2_u;
+
+typedef struct _disp_debug_t {
+     unsigned long disp_debug                     : 32;
+     } disp_debug_t;
+
+typedef union {
+     unsigned long val : 32;
+     disp_debug_t f;
+} disp_debug_u;
+
+typedef struct _disp_db_buf_cntl_rd_t {
+     unsigned long en_db_buf                      : 1;
+     unsigned long update_db_buf_done             : 1;
+     unsigned long db_buf_cntl                    : 6;
+     unsigned long                                : 24;
+     } disp_db_buf_cntl_rd_t;
+
+typedef union {
+     unsigned long val : 32;
+     disp_db_buf_cntl_rd_t f;
+} disp_db_buf_cntl_rd_u;
+
+typedef struct _disp_db_buf_cntl_wr_t {
+     unsigned long en_db_buf                      : 1;
+     unsigned long update_db_buf                  : 1;
+     unsigned long db_buf_cntl                    : 6;
+     unsigned long                                : 24;
+     } disp_db_buf_cntl_wr_t;
+
+typedef union {
+     unsigned long val : 32;
+     disp_db_buf_cntl_wr_t f;
+} disp_db_buf_cntl_wr_u;
+
+typedef struct _disp_crc_sig_t {
+     unsigned long crc_sig_r                      : 6;
+     unsigned long crc_sig_g                      : 6;
+     unsigned long crc_sig_b                      : 6;
+     unsigned long crc_cont_en                    : 1;
+     unsigned long crc_en                         : 1;
+     unsigned long crc_mask_en                    : 1;
+     unsigned long crc_sig_cntl                   : 6;
+     unsigned long                                : 5;
+     } disp_crc_sig_t;
+
+typedef union {
+     unsigned long val : 32;
+     disp_crc_sig_t f;
+} disp_crc_sig_u;
+
+typedef struct _crtc_default_count_t {
+     unsigned long crtc_hcount_def                : 10;
+     unsigned long                                : 6;
+     unsigned long crtc_vcount_def                : 10;
+     unsigned long                                : 6;
+     } crtc_default_count_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_default_count_t f;
+} crtc_default_count_u;
+
+typedef struct _lcd_background_color_t {
+     unsigned long lcd_bg_red                     : 8;
+     unsigned long lcd_bg_green                   : 8;
+     unsigned long lcd_bg_blue                    : 8;
+     unsigned long                                : 8;
+     } lcd_background_color_t;
+
+typedef union {
+     unsigned long val : 32;
+     lcd_background_color_t f;
+} lcd_background_color_u;
+
+typedef struct _crtc_ps2_t {
+     unsigned long ps2_start                      : 10;
+     unsigned long                                : 6;
+     unsigned long ps2_end                        : 10;
+     unsigned long                                : 4;
+     unsigned long ps2_pol                        : 1;
+     unsigned long ps2_en                         : 1;
+     } crtc_ps2_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_ps2_t f;
+} crtc_ps2_u;
+
+typedef struct _crtc_ps2_vpos_t {
+     unsigned long ps2_vpos_start                 : 10;
+     unsigned long                                : 6;
+     unsigned long ps2_vpos_end                   : 10;
+     unsigned long                                : 6;
+     } crtc_ps2_vpos_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_ps2_vpos_t f;
+} crtc_ps2_vpos_u;
+
+typedef struct _crtc_ps1_active_t {
+     unsigned long ps1_h_start                    : 10;
+     unsigned long                                : 6;
+     unsigned long ps1_h_end                      : 10;
+     unsigned long                                : 3;
+     unsigned long ps1_pol                        : 1;
+     unsigned long ps1_en                         : 1;
+     unsigned long ps1_use_nactive                : 1;
+     } crtc_ps1_active_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_ps1_active_t f;
+} crtc_ps1_active_u;
+
+typedef struct _crtc_ps1_nactive_t {
+     unsigned long ps1_h_start_na                 : 10;
+     unsigned long                                : 6;
+     unsigned long ps1_h_end_na                   : 10;
+     unsigned long                                : 5;
+     unsigned long ps1_en_na                      : 1;
+     } crtc_ps1_nactive_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_ps1_nactive_t f;
+} crtc_ps1_nactive_u;
+
+typedef struct _crtc_gclk_ext_t {
+     unsigned long gclk_alter_start               : 10;
+     unsigned long                                : 6;
+     unsigned long gclk_alter_width               : 2;
+     unsigned long gclk_en_alter                  : 1;
+     unsigned long gclk_db_width                  : 2;
+     unsigned long                                : 11;
+     } crtc_gclk_ext_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_gclk_ext_t f;
+} crtc_gclk_ext_u;
+
+typedef struct _crtc_alw_t {
+     unsigned long alw_hstart                     : 10;
+     unsigned long                                : 6;
+     unsigned long alw_hend                       : 10;
+     unsigned long                                : 4;
+     unsigned long alw_delay                      : 1;
+     unsigned long alw_en                         : 1;
+     } crtc_alw_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_alw_t f;
+} crtc_alw_u;
+
+typedef struct _crtc_alw_vpos_t {
+     unsigned long alw_vstart                     : 10;
+     unsigned long                                : 6;
+     unsigned long alw_vend                       : 10;
+     unsigned long                                : 6;
+     } crtc_alw_vpos_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_alw_vpos_t f;
+} crtc_alw_vpos_u;
+
+typedef struct _crtc_psk_t {
+     unsigned long psk_vstart                     : 10;
+     unsigned long                                : 6;
+     unsigned long psk_vend                       : 10;
+     unsigned long                                : 4;
+     unsigned long psk_pol                        : 1;
+     unsigned long psk_en                         : 1;
+     } crtc_psk_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_psk_t f;
+} crtc_psk_u;
+
+typedef struct _crtc_psk_hpos_t {
+     unsigned long psk_hstart                     : 10;
+     unsigned long                                : 6;
+     unsigned long psk_hend                       : 10;
+     unsigned long                                : 6;
+     } crtc_psk_hpos_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_psk_hpos_t f;
+} crtc_psk_hpos_u;
+
+typedef struct _crtc_cv4_start_t {
+     unsigned long cv4_vstart                     : 10;
+     unsigned long                                : 20;
+     unsigned long cv4_pol                        : 1;
+     unsigned long cv4_en                         : 1;
+     } crtc_cv4_start_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_cv4_start_t f;
+} crtc_cv4_start_u;
+
+typedef struct _crtc_cv4_end_t {
+     unsigned long cv4_vend1                      : 10;
+     unsigned long                                : 6;
+     unsigned long cv4_vend2                      : 10;
+     unsigned long                                : 6;
+     } crtc_cv4_end_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_cv4_end_t f;
+} crtc_cv4_end_u;
+
+typedef struct _crtc_cv4_hpos_t {
+     unsigned long cv4_hstart                     : 10;
+     unsigned long                                : 6;
+     unsigned long cv4_hend                       : 10;
+     unsigned long                                : 6;
+     } crtc_cv4_hpos_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_cv4_hpos_t f;
+} crtc_cv4_hpos_u;
+
+typedef struct _crtc_eck_t {
+     unsigned long eck_freq1                      : 3;
+     unsigned long eck_en                         : 1;
+     unsigned long                                : 28;
+     } crtc_eck_t;
+
+typedef union {
+     unsigned long val : 32;
+     crtc_eck_t f;
+} crtc_eck_u;
+
+typedef struct _refresh_cntl_t {
+     unsigned long ref_frame                      : 3;
+     unsigned long nref_frame                     : 5;
+     unsigned long ref_cntl                       : 1;
+     unsigned long stop_sm_nref                   : 1;
+     unsigned long stop_req_nref                  : 1;
+     unsigned long                                : 21;
+     } refresh_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     refresh_cntl_t f;
+} refresh_cntl_u;
+
+typedef struct _genlcd_cntl3_t {
+     unsigned long ps1_oe                         : 1;
+     unsigned long ps1_pd                         : 1;
+     unsigned long ps2_oe                         : 1;
+     unsigned long ps2_pd                         : 1;
+     unsigned long rev2_oe                        : 1;
+     unsigned long rev2_pd                        : 1;
+     unsigned long awl_oe                         : 1;
+     unsigned long awl_pd                         : 1;
+     unsigned long dinv_oe                        : 1;
+     unsigned long dinv_pd                        : 1;
+     unsigned long psk_out                        : 1;
+     unsigned long psd_out                        : 1;
+     unsigned long eck_out                        : 1;
+     unsigned long cv4_out                        : 1;
+     unsigned long ps1_out                        : 1;
+     unsigned long ps2_out                        : 1;
+     unsigned long rev_out                        : 1;
+     unsigned long rev2_out                       : 1;
+     unsigned long                                : 14;
+     } genlcd_cntl3_t;
+
+typedef union {
+     unsigned long val : 32;
+     genlcd_cntl3_t f;
+} genlcd_cntl3_u;
+
+typedef struct _gpio_data2_t {
+     unsigned long gio2_out                       : 16;
+     unsigned long gio2_in                        : 16;
+     } gpio_data2_t;
+
+typedef union {
+     unsigned long val : 32;
+     gpio_data2_t f;
+} gpio_data2_u;
+
+typedef struct _gpio_cntl3_t {
+     unsigned long gio2_pd                        : 16;
+     unsigned long gio2_schmen                    : 16;
+     } gpio_cntl3_t;
+
+typedef union {
+     unsigned long val : 32;
+     gpio_cntl3_t f;
+} gpio_cntl3_u;
+
+typedef struct _gpio_cntl4_t {
+     unsigned long gio2_oe                        : 16;
+     unsigned long                                : 16;
+     } gpio_cntl4_t;
+
+typedef union {
+     unsigned long val : 32;
+     gpio_cntl4_t f;
+} gpio_cntl4_u;
+
+typedef struct _chip_strap_t {
+     unsigned long config_strap                   : 8;
+     unsigned long pkg_strap                      : 1;
+     unsigned long                                : 23;
+     } chip_strap_t;
+
+typedef union {
+     unsigned long val : 32;
+     chip_strap_t f;
+} chip_strap_u;
+
+typedef struct _disp_debug2_t {
+     unsigned long disp_debug2                    : 32;
+     } disp_debug2_t;
+
+typedef union {
+     unsigned long val : 32;
+     disp_debug2_t f;
+} disp_debug2_u;
+
+typedef struct _debug_bus_cntl_t {
+     unsigned long debug_testmux                  : 4;
+     unsigned long debug_testsel                  : 4;
+     unsigned long debug_gioa_sel                 : 2;
+     unsigned long debug_giob_sel                 : 2;
+     unsigned long debug_clk_sel                  : 1;
+     unsigned long debug_clk_inv                  : 1;
+     unsigned long                                : 2;
+     unsigned long debug_bus                      : 16;
+     } debug_bus_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug_bus_cntl_t f;
+} debug_bus_cntl_u;
+
+typedef struct _gamma_value1_t {
+     unsigned long gamma1                         : 8;
+     unsigned long gamma2                         : 8;
+     unsigned long gamma3                         : 8;
+     unsigned long gamma4                         : 8;
+     } gamma_value1_t;
+
+typedef union {
+     unsigned long val : 32;
+     gamma_value1_t f;
+} gamma_value1_u;
+
+typedef struct _gamma_value2_t {
+     unsigned long gamma5                         : 8;
+     unsigned long gamma6                         : 8;
+     unsigned long gamma7                         : 8;
+     unsigned long gamma8                         : 8;
+     } gamma_value2_t;
+
+typedef union {
+     unsigned long val : 32;
+     gamma_value2_t f;
+} gamma_value2_u;
+
+typedef struct _gamma_slope_t {
+     unsigned long slope1                         : 3;
+     unsigned long slope2                         : 3;
+     unsigned long slope3                         : 3;
+     unsigned long slope4                         : 3;
+     unsigned long slope5                         : 3;
+     unsigned long slope6                         : 3;
+     unsigned long slope7                         : 3;
+     unsigned long slope8                         : 3;
+     unsigned long                                : 8;
+     } gamma_slope_t;
+
+typedef union {
+     unsigned long val : 32;
+     gamma_slope_t f;
+} gamma_slope_u;
+
+typedef struct _gen_status_t {
+     unsigned long status                         : 16;
+     unsigned long                                : 16;
+     } gen_status_t;
+
+typedef union {
+     unsigned long val : 32;
+     gen_status_t f;
+} gen_status_u;
+
+typedef struct _hw_int_t {
+     unsigned long hwint1_pos                     : 5;
+     unsigned long hwint2_pos                     : 5;
+     unsigned long hwint1_pol                     : 1;
+     unsigned long hwint2_pol                     : 1;
+     unsigned long hwint1_en_db                   : 1;
+     unsigned long hwint2_en_db                   : 1;
+     unsigned long                                : 18;
+     } hw_int_t;
+
+typedef union {
+     unsigned long val : 32;
+     hw_int_t f;
+} hw_int_u;
+
+typedef struct _dst_offset_t {
+     unsigned long dst_offset                     : 24;
+     unsigned long                                : 8;
+     } dst_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_offset_t f;
+} dst_offset_u;
+
+typedef struct _dst_pitch_t {
+     unsigned long dst_pitch                      : 14;
+     unsigned long mc_dst_pitch_mul               : 2;
+     unsigned long                                : 16;
+     } dst_pitch_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_pitch_t f;
+} dst_pitch_u;
+
+typedef struct _dst_pitch_offset_t {
+     unsigned long dst_offset                     : 20;
+     unsigned long dst_pitch                      : 10;
+     unsigned long mc_dst_pitch_mul               : 2;
+     } dst_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_pitch_offset_t f;
+} dst_pitch_offset_u;
+
+typedef struct _dst_x_t {
+     unsigned long dst_x                          : 14;
+     unsigned long                                : 18;
+     } dst_x_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_x_t f;
+} dst_x_u;
+
+typedef struct _dst_y_t {
+     unsigned long dst_y                          : 14;
+     unsigned long                                : 18;
+     } dst_y_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_y_t f;
+} dst_y_u;
+
+typedef struct _dst_x_y_t {
+     unsigned long dst_y                          : 14;
+     unsigned long                                : 2;
+     unsigned long dst_x                          : 14;
+     unsigned long                                : 2;
+     } dst_x_y_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_x_y_t f;
+} dst_x_y_u;
+
+typedef struct _dst_y_x_t {
+     unsigned long dst_x                          : 14;
+     unsigned long                                : 2;
+     unsigned long dst_y                          : 14;
+     unsigned long                                : 2;
+     } dst_y_x_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_y_x_t f;
+} dst_y_x_u;
+
+typedef struct _dst_width_t {
+     unsigned long dst_width_b0                   : 8;
+     unsigned long dst_width_b1                   : 6;
+     unsigned long                                : 18;
+     } dst_width_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_width_t f;
+} dst_width_u;
+
+typedef struct _dst_height_t {
+     unsigned long dst_height                     : 14;
+     unsigned long                                : 18;
+     } dst_height_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_height_t f;
+} dst_height_u;
+
+typedef struct _dst_width_height_t {
+     unsigned long dst_height                     : 14;
+     unsigned long                                : 2;
+     unsigned long dst_width_b0                   : 8;
+     unsigned long dst_width_b1                   : 6;
+     unsigned long                                : 2;
+     } dst_width_height_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_width_height_t f;
+} dst_width_height_u;
+
+typedef struct _dst_height_width_t {
+     unsigned long dst_width_b0                   : 8;
+     unsigned long dst_width_b1                   : 6;
+     unsigned long                                : 2;
+     unsigned long dst_height                     : 14;
+     unsigned long                                : 2;
+     } dst_height_width_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_height_width_t f;
+} dst_height_width_u;
+
+typedef struct _dst_height_width_8_t {
+     unsigned long                                : 16;
+     unsigned long dst_width_b0                   : 8;
+     unsigned long dst_height                     : 8;
+     } dst_height_width_8_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_height_width_8_t f;
+} dst_height_width_8_u;
+
+typedef struct _dst_height_y_t {
+     unsigned long dst_y                          : 14;
+     unsigned long                                : 2;
+     unsigned long dst_height                     : 14;
+     unsigned long                                : 2;
+     } dst_height_y_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_height_y_t f;
+} dst_height_y_u;
+
+typedef struct _dst_width_x_t {
+     unsigned long dst_x                          : 14;
+     unsigned long                                : 2;
+     unsigned long dst_width_b0                   : 8;
+     unsigned long dst_width_b1                   : 6;
+     unsigned long                                : 2;
+     } dst_width_x_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_width_x_t f;
+} dst_width_x_u;
+
+typedef struct _dst_width_x_incy_t {
+     unsigned long dst_x                          : 14;
+     unsigned long                                : 2;
+     unsigned long dst_width_b0                   : 8;
+     unsigned long dst_width_b1                   : 6;
+     unsigned long                                : 2;
+     } dst_width_x_incy_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_width_x_incy_t f;
+} dst_width_x_incy_u;
+
+typedef struct _dst_line_start_t {
+     unsigned long dst_start_x                    : 14;
+     unsigned long                                : 2;
+     unsigned long dst_start_y                    : 14;
+     unsigned long                                : 2;
+     } dst_line_start_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_line_start_t f;
+} dst_line_start_u;
+
+typedef struct _dst_line_end_t {
+     unsigned long dst_end_x                      : 14;
+     unsigned long                                : 2;
+     unsigned long dst_end_y_b0                   : 8;
+     unsigned long dst_end_y_b1                   : 6;
+     unsigned long                                : 2;
+     } dst_line_end_t;
+
+typedef union {
+     unsigned long val : 32;
+     dst_line_end_t f;
+} dst_line_end_u;
+
+typedef struct _brush_offset_t {
+     unsigned long brush_offset                   : 24;
+     unsigned long                                : 8;
+     } brush_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     brush_offset_t f;
+} brush_offset_u;
+
+typedef struct _brush_y_x_t {
+     unsigned long brush_x                        : 5;
+     unsigned long                                : 3;
+     unsigned long brush_y                        : 3;
+     unsigned long                                : 21;
+     } brush_y_x_t;
+
+typedef union {
+     unsigned long val : 32;
+     brush_y_x_t f;
+} brush_y_x_u;
+
+typedef struct _dp_brush_frgd_clr_t {
+     unsigned long dp_brush_frgd_clr              : 32;
+     } dp_brush_frgd_clr_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_brush_frgd_clr_t f;
+} dp_brush_frgd_clr_u;
+
+typedef struct _dp_brush_bkgd_clr_t {
+     unsigned long dp_brush_bkgd_clr              : 32;
+     } dp_brush_bkgd_clr_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_brush_bkgd_clr_t f;
+} dp_brush_bkgd_clr_u;
+
+typedef struct _src2_offset_t {
+     unsigned long src2_offset                    : 24;
+     unsigned long                                : 8;
+     } src2_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_offset_t f;
+} src2_offset_u;
+
+typedef struct _src2_pitch_t {
+     unsigned long src2_pitch                     : 14;
+     unsigned long src2_pitch_mul                 : 2;
+     unsigned long                                : 16;
+     } src2_pitch_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_pitch_t f;
+} src2_pitch_u;
+
+typedef struct _src2_pitch_offset_t {
+     unsigned long src2_offset                    : 20;
+     unsigned long                                : 2;
+     unsigned long src2_pitch                     : 8;
+     unsigned long src2_pitch_mul                 : 2;
+     } src2_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_pitch_offset_t f;
+} src2_pitch_offset_u;
+
+typedef struct _src2_x_t {
+     unsigned long src_x                          : 14;
+     unsigned long                                : 18;
+     } src2_x_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_x_t f;
+} src2_x_u;
+
+typedef struct _src2_y_t {
+     unsigned long src_y                          : 14;
+     unsigned long                                : 18;
+     } src2_y_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_y_t f;
+} src2_y_u;
+
+typedef struct _src2_x_y_t {
+     unsigned long src_y                          : 14;
+     unsigned long                                : 2;
+     unsigned long src_x                          : 14;
+     unsigned long                                : 2;
+     } src2_x_y_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_x_y_t f;
+} src2_x_y_u;
+
+typedef struct _src2_width_t {
+     unsigned long src2_width                     : 14;
+     unsigned long                                : 18;
+     } src2_width_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_width_t f;
+} src2_width_u;
+
+typedef struct _src2_height_t {
+     unsigned long src2_height                    : 14;
+     unsigned long                                : 18;
+     } src2_height_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_height_t f;
+} src2_height_u;
+
+typedef struct _src2_inc_t {
+     unsigned long src2_xinc                      : 6;
+     unsigned long                                : 2;
+     unsigned long src2_yinc                      : 6;
+     unsigned long                                : 18;
+     } src2_inc_t;
+
+typedef union {
+     unsigned long val : 32;
+     src2_inc_t f;
+} src2_inc_u;
+
+typedef struct _src_offset_t {
+     unsigned long src_offset                     : 24;
+     unsigned long                                : 8;
+     } src_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_offset_t f;
+} src_offset_u;
+
+typedef struct _src_pitch_t {
+     unsigned long src_pitch                      : 14;
+     unsigned long src_pitch_mul                  : 2;
+     unsigned long                                : 16;
+     } src_pitch_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_pitch_t f;
+} src_pitch_u;
+
+typedef struct _src_pitch_offset_t {
+     unsigned long src_offset                     : 20;
+     unsigned long src_pitch                      : 10;
+     unsigned long src_pitch_mul                  : 2;
+     } src_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_pitch_offset_t f;
+} src_pitch_offset_u;
+
+typedef struct _src_x_t {
+     unsigned long src_x                          : 14;
+     unsigned long                                : 18;
+     } src_x_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_x_t f;
+} src_x_u;
+
+typedef struct _src_y_t {
+     unsigned long src_y                          : 14;
+     unsigned long                                : 18;
+     } src_y_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_y_t f;
+} src_y_u;
+
+typedef struct _src_x_y_t {
+     unsigned long src_y                          : 14;
+     unsigned long                                : 2;
+     unsigned long src_x                          : 14;
+     unsigned long                                : 2;
+     } src_x_y_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_x_y_t f;
+} src_x_y_u;
+
+typedef struct _src_y_x_t {
+     unsigned long src_x                          : 14;
+     unsigned long                                : 2;
+     unsigned long src_y                          : 14;
+     unsigned long                                : 2;
+     } src_y_x_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_y_x_t f;
+} src_y_x_u;
+
+typedef struct _src_width_t {
+     unsigned long src_width                      : 14;
+     unsigned long                                : 18;
+     } src_width_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_width_t f;
+} src_width_u;
+
+typedef struct _src_height_t {
+     unsigned long src_height                     : 14;
+     unsigned long                                : 18;
+     } src_height_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_height_t f;
+} src_height_u;
+
+typedef struct _src_inc_t {
+     unsigned long src_xinc                       : 6;
+     unsigned long                                : 2;
+     unsigned long src_yinc                       : 6;
+     unsigned long                                : 18;
+     } src_inc_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_inc_t f;
+} src_inc_u;
+
+typedef struct _host_data0_t {
+     unsigned long host_data                      : 32;
+     } host_data0_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data0_t f;
+} host_data0_u;
+
+typedef struct _host_data1_t {
+     unsigned long host_data                      : 32;
+     } host_data1_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data1_t f;
+} host_data1_u;
+
+typedef struct _host_data2_t {
+     unsigned long host_data                      : 32;
+     } host_data2_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data2_t f;
+} host_data2_u;
+
+typedef struct _host_data3_t {
+     unsigned long host_data                      : 32;
+     } host_data3_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data3_t f;
+} host_data3_u;
+
+typedef struct _host_data4_t {
+     unsigned long host_data                      : 32;
+     } host_data4_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data4_t f;
+} host_data4_u;
+
+typedef struct _host_data5_t {
+     unsigned long host_data                      : 32;
+     } host_data5_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data5_t f;
+} host_data5_u;
+
+typedef struct _host_data6_t {
+     unsigned long host_data                      : 32;
+     } host_data6_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data6_t f;
+} host_data6_u;
+
+typedef struct _host_data7_t {
+     unsigned long host_data                      : 32;
+     } host_data7_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data7_t f;
+} host_data7_u;
+
+typedef struct _host_data_last_t {
+     unsigned long host_data_last                 : 32;
+     } host_data_last_t;
+
+typedef union {
+     unsigned long val : 32;
+     host_data_last_t f;
+} host_data_last_u;
+
+typedef struct _dp_src_frgd_clr_t {
+     unsigned long dp_src_frgd_clr                : 32;
+     } dp_src_frgd_clr_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_src_frgd_clr_t f;
+} dp_src_frgd_clr_u;
+
+typedef struct _dp_src_bkgd_clr_t {
+     unsigned long dp_src_bkgd_clr                : 32;
+     } dp_src_bkgd_clr_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_src_bkgd_clr_t f;
+} dp_src_bkgd_clr_u;
+
+typedef struct _sc_left_t {
+     unsigned long sc_left                        : 14;
+     unsigned long                                : 18;
+     } sc_left_t;
+
+typedef union {
+     unsigned long val : 32;
+     sc_left_t f;
+} sc_left_u;
+
+typedef struct _sc_right_t {
+     unsigned long sc_right                       : 14;
+     unsigned long                                : 18;
+     } sc_right_t;
+
+typedef union {
+     unsigned long val : 32;
+     sc_right_t f;
+} sc_right_u;
+
+typedef struct _sc_top_t {
+     unsigned long sc_top                         : 14;
+     unsigned long                                : 18;
+     } sc_top_t;
+
+typedef union {
+     unsigned long val : 32;
+     sc_top_t f;
+} sc_top_u;
+
+typedef struct _sc_bottom_t {
+     unsigned long sc_bottom                      : 14;
+     unsigned long                                : 18;
+     } sc_bottom_t;
+
+typedef union {
+     unsigned long val : 32;
+     sc_bottom_t f;
+} sc_bottom_u;
+
+typedef struct _src_sc_right_t {
+     unsigned long sc_right                       : 14;
+     unsigned long                                : 18;
+     } src_sc_right_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_sc_right_t f;
+} src_sc_right_u;
+
+typedef struct _src_sc_bottom_t {
+     unsigned long sc_bottom                      : 14;
+     unsigned long                                : 18;
+     } src_sc_bottom_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_sc_bottom_t f;
+} src_sc_bottom_u;
+
+typedef struct _dp_cntl_t {
+     unsigned long dst_x_dir                      : 1;
+     unsigned long dst_y_dir                      : 1;
+     unsigned long src_x_dir                      : 1;
+     unsigned long src_y_dir                      : 1;
+     unsigned long dst_major_x                    : 1;
+     unsigned long src_major_x                    : 1;
+     unsigned long                                : 26;
+     } dp_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_cntl_t f;
+} dp_cntl_u;
+
+typedef struct _dp_cntl_dst_dir_t {
+     unsigned long                                : 15;
+     unsigned long dst_y_dir                      : 1;
+     unsigned long                                : 15;
+     unsigned long dst_x_dir                      : 1;
+     } dp_cntl_dst_dir_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_cntl_dst_dir_t f;
+} dp_cntl_dst_dir_u;
+
+typedef struct _dp_datatype_t {
+     unsigned long dp_dst_datatype                : 4;
+     unsigned long                                : 4;
+     unsigned long dp_brush_datatype              : 4;
+     unsigned long dp_src2_type                   : 1;
+     unsigned long dp_src2_datatype               : 3;
+     unsigned long dp_src_datatype                : 3;
+     unsigned long                                : 11;
+     unsigned long dp_byte_pix_order              : 1;
+     unsigned long                                : 1;
+     } dp_datatype_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_datatype_t f;
+} dp_datatype_u;
+
+typedef struct _dp_mix_t {
+     unsigned long                                : 8;
+     unsigned long dp_src_source                  : 3;
+     unsigned long dp_src2_source                 : 3;
+     unsigned long                                : 2;
+     unsigned long dp_rop3                        : 8;
+     unsigned long dp_op                          : 1;
+     unsigned long                                : 7;
+     } dp_mix_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_mix_t f;
+} dp_mix_u;
+
+typedef struct _dp_write_msk_t {
+     unsigned long dp_write_msk                   : 32;
+     } dp_write_msk_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_write_msk_t f;
+} dp_write_msk_u;
+
+typedef struct _clr_cmp_clr_src_t {
+     unsigned long clr_cmp_clr_src                : 32;
+     } clr_cmp_clr_src_t;
+
+typedef union {
+     unsigned long val : 32;
+     clr_cmp_clr_src_t f;
+} clr_cmp_clr_src_u;
+
+typedef struct _clr_cmp_clr_dst_t {
+     unsigned long clr_cmp_clr_dst                : 32;
+     } clr_cmp_clr_dst_t;
+
+typedef union {
+     unsigned long val : 32;
+     clr_cmp_clr_dst_t f;
+} clr_cmp_clr_dst_u;
+
+typedef struct _clr_cmp_cntl_t {
+     unsigned long clr_cmp_fcn_src                : 3;
+     unsigned long                                : 5;
+     unsigned long clr_cmp_fcn_dst                : 3;
+     unsigned long                                : 13;
+     unsigned long clr_cmp_src                    : 2;
+     unsigned long                                : 6;
+     } clr_cmp_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     clr_cmp_cntl_t f;
+} clr_cmp_cntl_u;
+
+typedef struct _clr_cmp_msk_t {
+     unsigned long clr_cmp_msk                    : 32;
+     } clr_cmp_msk_t;
+
+typedef union {
+     unsigned long val : 32;
+     clr_cmp_msk_t f;
+} clr_cmp_msk_u;
+
+typedef struct _default_pitch_offset_t {
+     unsigned long default_offset                 : 20;
+     unsigned long default_pitch                  : 10;
+     unsigned long                                : 2;
+     } default_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     default_pitch_offset_t f;
+} default_pitch_offset_u;
+
+typedef struct _default_sc_bottom_right_t {
+     unsigned long default_sc_right               : 14;
+     unsigned long                                : 2;
+     unsigned long default_sc_bottom              : 14;
+     unsigned long                                : 2;
+     } default_sc_bottom_right_t;
+
+typedef union {
+     unsigned long val : 32;
+     default_sc_bottom_right_t f;
+} default_sc_bottom_right_u;
+
+typedef struct _default2_sc_bottom_right_t {
+     unsigned long default_sc_right               : 14;
+     unsigned long                                : 2;
+     unsigned long default_sc_bottom              : 14;
+     unsigned long                                : 2;
+     } default2_sc_bottom_right_t;
+
+typedef union {
+     unsigned long val : 32;
+     default2_sc_bottom_right_t f;
+} default2_sc_bottom_right_u;
+
+typedef struct _ref1_pitch_offset_t {
+     unsigned long offset                         : 20;
+     unsigned long                                : 2;
+     unsigned long pitch                          : 8;
+     unsigned long                                : 2;
+     } ref1_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     ref1_pitch_offset_t f;
+} ref1_pitch_offset_u;
+
+typedef struct _ref2_pitch_offset_t {
+     unsigned long offset                         : 20;
+     unsigned long                                : 2;
+     unsigned long pitch                          : 8;
+     unsigned long                                : 2;
+     } ref2_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     ref2_pitch_offset_t f;
+} ref2_pitch_offset_u;
+
+typedef struct _ref3_pitch_offset_t {
+     unsigned long offset                         : 20;
+     unsigned long                                : 2;
+     unsigned long pitch                          : 8;
+     unsigned long                                : 2;
+     } ref3_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     ref3_pitch_offset_t f;
+} ref3_pitch_offset_u;
+
+typedef struct _ref4_pitch_offset_t {
+     unsigned long offset                         : 20;
+     unsigned long                                : 2;
+     unsigned long pitch                          : 8;
+     unsigned long                                : 2;
+     } ref4_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     ref4_pitch_offset_t f;
+} ref4_pitch_offset_u;
+
+typedef struct _ref5_pitch_offset_t {
+     unsigned long offset                         : 20;
+     unsigned long                                : 2;
+     unsigned long pitch                          : 8;
+     unsigned long                                : 2;
+     } ref5_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     ref5_pitch_offset_t f;
+} ref5_pitch_offset_u;
+
+typedef struct _ref6_pitch_offset_t {
+     unsigned long offset                         : 20;
+     unsigned long                                : 2;
+     unsigned long pitch                          : 8;
+     unsigned long                                : 2;
+     } ref6_pitch_offset_t;
+
+typedef union {
+     unsigned long val : 32;
+     ref6_pitch_offset_t f;
+} ref6_pitch_offset_u;
+
+typedef struct _dp_gui_master_cntl_t {
+     unsigned long gmc_src_pitch_offset_cntl      : 1;
+     unsigned long gmc_dst_pitch_offset_cntl      : 1;
+     unsigned long gmc_src_clipping               : 1;
+     unsigned long gmc_dst_clipping               : 1;
+     unsigned long gmc_brush_datatype             : 4;
+     unsigned long gmc_dst_datatype               : 4;
+     unsigned long gmc_src_datatype               : 3;
+     unsigned long gmc_byte_pix_order             : 1;
+     unsigned long gmc_default_sel                : 1;
+     unsigned long gmc_rop3                       : 8;
+     unsigned long gmc_dp_src_source              : 3;
+     unsigned long gmc_clr_cmp_fcn_dis            : 1;
+     unsigned long                                : 1;
+     unsigned long gmc_wr_msk_dis                 : 1;
+     unsigned long gmc_dp_op                      : 1;
+     } dp_gui_master_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     dp_gui_master_cntl_t f;
+} dp_gui_master_cntl_u;
+
+typedef struct _sc_top_left_t {
+     unsigned long sc_left                        : 14;
+     unsigned long                                : 2;
+     unsigned long sc_top                         : 14;
+     unsigned long                                : 2;
+     } sc_top_left_t;
+
+typedef union {
+     unsigned long val : 32;
+     sc_top_left_t f;
+} sc_top_left_u;
+
+typedef struct _sc_bottom_right_t {
+     unsigned long sc_right                       : 14;
+     unsigned long                                : 2;
+     unsigned long sc_bottom                      : 14;
+     unsigned long                                : 2;
+     } sc_bottom_right_t;
+
+typedef union {
+     unsigned long val : 32;
+     sc_bottom_right_t f;
+} sc_bottom_right_u;
+
+typedef struct _src_sc_bottom_right_t {
+     unsigned long sc_right                       : 14;
+     unsigned long                                : 2;
+     unsigned long sc_bottom                      : 14;
+     unsigned long                                : 2;
+     } src_sc_bottom_right_t;
+
+typedef union {
+     unsigned long val : 32;
+     src_sc_bottom_right_t f;
+} src_sc_bottom_right_u;
+
+typedef struct _global_alpha_t {
+     unsigned long alpha_r                        : 8;
+     unsigned long alpha_g                        : 8;
+     unsigned long alpha_b                        : 8;
+     unsigned long alpha_a                        : 8;
+     } global_alpha_t;
+
+typedef union {
+     unsigned long val : 32;
+     global_alpha_t f;
+} global_alpha_u;
+
+typedef struct _filter_coef_t {
+     unsigned long c_4                            : 4;
+     unsigned long c_3                            : 4;
+     unsigned long c_2                            : 4;
+     unsigned long c_1                            : 4;
+     unsigned long c1                             : 4;
+     unsigned long c2                             : 4;
+     unsigned long c3                             : 4;
+     unsigned long c4                             : 4;
+     } filter_coef_t;
+
+typedef union {
+     unsigned long val : 32;
+     filter_coef_t f;
+} filter_coef_u;
+
+typedef struct _mvc_cntl_start_t {
+     unsigned long mc_cntl_src_1_index            : 4;
+     unsigned long mc_cntl_dst_offset             : 20;
+     unsigned long mc_dst_pitch_mul               : 2;
+     unsigned long mc_cntl_src_2_index            : 3;
+     unsigned long mc_cntl_width_height_sel       : 3;
+     } mvc_cntl_start_t;
+
+typedef union {
+     unsigned long val : 32;
+     mvc_cntl_start_t f;
+} mvc_cntl_start_u;
+
+typedef struct _e2_arithmetic_cntl_t {
+     unsigned long opcode                         : 5;
+     unsigned long shiftright                     : 4;
+     unsigned long clamp                          : 1;
+     unsigned long rounding                       : 2;
+     unsigned long filter_n                       : 3;
+     unsigned long                                : 1;
+     unsigned long srcblend_inv                   : 1;
+     unsigned long srcblend                       : 4;
+     unsigned long                                : 3;
+     unsigned long dstblend_inv                   : 1;
+     unsigned long dstblend                       : 4;
+     unsigned long dst_signed                     : 1;
+     unsigned long autoinc                        : 1;
+     unsigned long                                : 1;
+     } e2_arithmetic_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     e2_arithmetic_cntl_t f;
+} e2_arithmetic_cntl_u;
+
+typedef struct _debug0_t {
+     unsigned long debug0_r                       : 8;
+     unsigned long                                : 8;
+     unsigned long debug0_rw                      : 8;
+     unsigned long                                : 8;
+     } debug0_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug0_t f;
+} debug0_u;
+
+typedef struct _debug1_t {
+     unsigned long debug1_r                       : 8;
+     unsigned long                                : 8;
+     unsigned long debug1_rw                      : 8;
+     unsigned long                                : 8;
+     } debug1_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug1_t f;
+} debug1_u;
+
+typedef struct _debug2_t {
+     unsigned long debug2_r                       : 8;
+     unsigned long                                : 8;
+     unsigned long debug2_rw                      : 8;
+     unsigned long                                : 8;
+     } debug2_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug2_t f;
+} debug2_u;
+
+typedef struct _debug3_t {
+     unsigned long                                : 32;
+     } debug3_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug3_t f;
+} debug3_u;
+
+typedef struct _debug4_t {
+     unsigned long                                : 32;
+     } debug4_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug4_t f;
+} debug4_u;
+
+typedef struct _debug5_t {
+     unsigned long                                : 32;
+     } debug5_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug5_t f;
+} debug5_u;
+
+typedef struct _debug6_t {
+     unsigned long                                : 32;
+     } debug6_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug6_t f;
+} debug6_u;
+
+typedef struct _debug7_t {
+     unsigned long                                : 32;
+     } debug7_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug7_t f;
+} debug7_u;
+
+typedef struct _debug8_t {
+     unsigned long                                : 32;
+     } debug8_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug8_t f;
+} debug8_u;
+
+typedef struct _debug9_t {
+     unsigned long                                : 32;
+     } debug9_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug9_t f;
+} debug9_u;
+
+typedef struct _debug10_t {
+     unsigned long                                : 32;
+     } debug10_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug10_t f;
+} debug10_u;
+
+typedef struct _debug11_t {
+     unsigned long                                : 32;
+     } debug11_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug11_t f;
+} debug11_u;
+
+typedef struct _debug12_t {
+     unsigned long                                : 32;
+     } debug12_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug12_t f;
+} debug12_u;
+
+typedef struct _debug13_t {
+     unsigned long                                : 32;
+     } debug13_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug13_t f;
+} debug13_u;
+
+typedef struct _debug14_t {
+     unsigned long                                : 32;
+     } debug14_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug14_t f;
+} debug14_u;
+
+typedef struct _debug15_t {
+     unsigned long                                : 32;
+     } debug15_t;
+
+typedef union {
+     unsigned long val : 32;
+     debug15_t f;
+} debug15_u;
+
+typedef struct _eng_cntl_t {
+     unsigned long erc_reg_rd_ws                  : 1;
+     unsigned long erc_reg_wr_ws                  : 1;
+     unsigned long erc_idle_reg_wr                : 1;
+     unsigned long dis_engine_triggers            : 1;
+     unsigned long dis_rop_src_uses_dst_w_h       : 1;
+     unsigned long dis_src_uses_dst_dirmaj        : 1;
+     unsigned long                                : 6;
+     unsigned long force_3dclk_when_2dclk         : 1;
+     unsigned long                                : 19;
+     } eng_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     eng_cntl_t f;
+} eng_cntl_u;
+
+typedef struct _eng_perf_cnt_t {
+     unsigned long perf_cnt                       : 20;
+     unsigned long perf_sel                       : 4;
+     unsigned long perf_en                        : 1;
+     unsigned long                                : 3;
+     unsigned long perf_clr                       : 1;
+     unsigned long                                : 3;
+     } eng_perf_cnt_t;
+
+typedef union {
+     unsigned long val : 32;
+     eng_perf_cnt_t f;
+} eng_perf_cnt_u;
+
+typedef struct _idct_runs_t {
+     unsigned long idct_runs_3                    : 8;
+     unsigned long idct_runs_2                    : 8;
+     unsigned long idct_runs_1                    : 8;
+     unsigned long idct_runs_0                    : 8;
+     } idct_runs_t;
+
+typedef union {
+     unsigned long val : 32;
+     idct_runs_t f;
+} idct_runs_u;
+
+typedef struct _idct_levels_t {
+     unsigned long idct_level_hi                  : 16;
+     unsigned long idct_level_lo                  : 16;
+     } idct_levels_t;
+
+typedef union {
+     unsigned long val : 32;
+     idct_levels_t f;
+} idct_levels_u;
+
+typedef struct _idct_control_t {
+     unsigned long idct_ctl_luma_rd_format        : 2;
+     unsigned long idct_ctl_chroma_rd_format      : 2;
+     unsigned long idct_ctl_scan_pattern          : 1;
+     unsigned long idct_ctl_intra                 : 1;
+     unsigned long idct_ctl_flush                 : 1;
+     unsigned long idct_ctl_passthru              : 1;
+     unsigned long idct_ctl_sw_reset              : 1;
+     unsigned long idct_ctl_constreq              : 1;
+     unsigned long idct_ctl_scramble              : 1;
+     unsigned long idct_ctl_alt_scan              : 1;
+     unsigned long                                : 20;
+     } idct_control_t;
+
+typedef union {
+     unsigned long val : 32;
+     idct_control_t f;
+} idct_control_u;
+
+typedef struct _idct_auth_control_t {
+     unsigned long control_bits                   : 32;
+     } idct_auth_control_t;
+
+typedef union {
+     unsigned long val : 32;
+     idct_auth_control_t f;
+} idct_auth_control_u;
+
+typedef struct _idct_auth_t {
+     unsigned long auth                           : 32;
+     } idct_auth_t;
+
+typedef union {
+     unsigned long val : 32;
+     idct_auth_t f;
+} idct_auth_u;
+
+typedef struct _mem_cntl_t {
+     unsigned long                                : 1;
+     unsigned long en_mem_ch1                     : 1;
+     unsigned long en_mem_ch2                     : 1;
+     unsigned long int_mem_mapping                : 1;
+     unsigned long                                : 28;
+     } mem_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     mem_cntl_t f;
+} mem_cntl_u;
+
+typedef struct _mem_arb_t {
+     unsigned long disp_time_slot                 : 4;
+     unsigned long disp_timer                     : 4;
+     unsigned long arb_option                     : 1;
+     unsigned long                                : 23;
+     } mem_arb_t;
+
+typedef union {
+     unsigned long val : 32;
+     mem_arb_t f;
+} mem_arb_u;
+
+typedef struct _mc_fb_location_t {
+     unsigned long mc_fb_start                    : 16;
+     unsigned long mc_fb_top                      : 16;
+     } mc_fb_location_t;
+
+typedef union {
+     unsigned long val : 32;
+     mc_fb_location_t f;
+} mc_fb_location_u;
+
+typedef struct _mem_ext_cntl_t {
+     unsigned long mem_ext_enable                 : 1;
+     unsigned long mem_ap_enable                  : 1;
+     unsigned long mem_addr_mapping               : 2;
+     unsigned long mem_wdoe_cntl                  : 2;
+     unsigned long mem_wdoe_extend                : 1;
+     unsigned long                                : 1;
+     unsigned long mem_page_timer                 : 8;
+     unsigned long mem_dynamic_cke                : 1;
+     unsigned long mem_sdram_tri_en               : 1;
+     unsigned long mem_self_refresh_en            : 1;
+     unsigned long mem_power_down                 : 1;
+     unsigned long mem_hw_power_down_en           : 1;
+     unsigned long mem_power_down_stat            : 1;
+     unsigned long                                : 3;
+     unsigned long mem_pd_mck                     : 1;
+     unsigned long mem_pd_ma                      : 1;
+     unsigned long mem_pd_mdq                     : 1;
+     unsigned long mem_tristate_mck               : 1;
+     unsigned long mem_tristate_ma                : 1;
+     unsigned long mem_tristate_mcke              : 1;
+     unsigned long mem_invert_mck                 : 1;
+     } mem_ext_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     mem_ext_cntl_t f;
+} mem_ext_cntl_u;
+
+typedef struct _mc_ext_mem_location_t {
+     unsigned long mc_ext_mem_start               : 16;
+     unsigned long mc_ext_mem_top                 : 16;
+     } mc_ext_mem_location_t;
+
+typedef union {
+     unsigned long val : 32;
+     mc_ext_mem_location_t f;
+} mc_ext_mem_location_u;
+
+typedef struct _mem_ext_timing_cntl_t {
+     unsigned long mem_trp                        : 2;
+     unsigned long mem_trcd                       : 2;
+     unsigned long mem_tras                       : 3;
+     unsigned long                                : 1;
+     unsigned long mem_trrd                       : 2;
+     unsigned long mem_tr2w                       : 2;
+     unsigned long mem_twr                        : 2;
+     unsigned long                                : 4;
+     unsigned long mem_twr_mode                   : 1;
+     unsigned long                                : 1;
+     unsigned long mem_refresh_dis                : 1;
+     unsigned long                                : 3;
+     unsigned long mem_refresh_rate               : 8;
+     } mem_ext_timing_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     mem_ext_timing_cntl_t f;
+} mem_ext_timing_cntl_u;
+
+typedef struct _mem_sdram_mode_reg_t {
+     unsigned long mem_mode_reg                   : 14;
+     unsigned long                                : 2;
+     unsigned long mem_read_latency               : 2;
+     unsigned long mem_schmen_latency             : 2;
+     unsigned long mem_cas_latency                : 2;
+     unsigned long mem_schmen_extend              : 1;
+     unsigned long                                : 8;
+     unsigned long mem_sdram_reset                : 1;
+     } mem_sdram_mode_reg_t;
+
+typedef union {
+     unsigned long val : 32;
+     mem_sdram_mode_reg_t f;
+} mem_sdram_mode_reg_u;
+
+typedef struct _mem_io_cntl_t {
+     unsigned long mem_sn_mck                     : 4;
+     unsigned long mem_sn_ma                      : 4;
+     unsigned long mem_sn_mdq                     : 4;
+     unsigned long mem_srn_mck                    : 1;
+     unsigned long mem_srn_ma                     : 1;
+     unsigned long mem_srn_mdq                    : 1;
+     unsigned long                                : 1;
+     unsigned long mem_sp_mck                     : 4;
+     unsigned long mem_sp_ma                      : 4;
+     unsigned long mem_sp_mdq                     : 4;
+     unsigned long mem_srp_mck                    : 1;
+     unsigned long mem_srp_ma                     : 1;
+     unsigned long mem_srp_mdq                    : 1;
+     unsigned long                                : 1;
+     } mem_io_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     mem_io_cntl_t f;
+} mem_io_cntl_u;
+
+typedef struct _mc_debug_t {
+     unsigned long mc_debug                       : 32;
+     } mc_debug_t;
+
+typedef union {
+     unsigned long val : 32;
+     mc_debug_t f;
+} mc_debug_u;
+
+typedef struct _mc_bist_ctrl_t {
+     unsigned long mc_bist_ctrl                   : 32;
+     } mc_bist_ctrl_t;
+
+typedef union {
+     unsigned long val : 32;
+     mc_bist_ctrl_t f;
+} mc_bist_ctrl_u;
+
+typedef struct _mc_bist_collar_read_t {
+     unsigned long mc_bist_collar_read            : 32;
+     } mc_bist_collar_read_t;
+
+typedef union {
+     unsigned long val : 32;
+     mc_bist_collar_read_t f;
+} mc_bist_collar_read_u;
+
+typedef struct _tc_mismatch_t {
+     unsigned long tc_mismatch                    : 24;
+     unsigned long                                : 8;
+     } tc_mismatch_t;
+
+typedef union {
+     unsigned long val : 32;
+     tc_mismatch_t f;
+} tc_mismatch_u;
+
+typedef struct _mc_perf_mon_cntl_t {
+     unsigned long clr_perf                       : 1;
+     unsigned long en_perf                        : 1;
+     unsigned long                                : 2;
+     unsigned long perf_op_a                      : 2;
+     unsigned long perf_op_b                      : 2;
+     unsigned long                                : 8;
+     unsigned long monitor_period                 : 8;
+     unsigned long perf_count_a_overflow          : 1;
+     unsigned long perf_count_b_overflow          : 1;
+     unsigned long                                : 6;
+     } mc_perf_mon_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     mc_perf_mon_cntl_t f;
+} mc_perf_mon_cntl_u;
+
+typedef struct _mc_perf_counters_t {
+     unsigned long mc_perf_counter_a              : 16;
+     unsigned long mc_perf_counter_b              : 16;
+     } mc_perf_counters_t;
+
+typedef union {
+     unsigned long val : 32;
+     mc_perf_counters_t f;
+} mc_perf_counters_u;
+
+typedef struct _wait_until_t {
+     unsigned long wait_crtc_pflip                : 1;
+     unsigned long wait_re_crtc_vline             : 1;
+     unsigned long wait_fe_crtc_vline             : 1;
+     unsigned long wait_crtc_vline                : 1;
+     unsigned long wait_dma_viph0_idle            : 1;
+     unsigned long wait_dma_viph1_idle            : 1;
+     unsigned long wait_dma_viph2_idle            : 1;
+     unsigned long wait_dma_viph3_idle            : 1;
+     unsigned long wait_dma_vid_idle              : 1;
+     unsigned long wait_dma_gui_idle              : 1;
+     unsigned long wait_cmdfifo                   : 1;
+     unsigned long wait_ov0_flip                  : 1;
+     unsigned long wait_ov0_slicedone             : 1;
+     unsigned long                                : 1;
+     unsigned long wait_2d_idle                   : 1;
+     unsigned long wait_3d_idle                   : 1;
+     unsigned long wait_2d_idleclean              : 1;
+     unsigned long wait_3d_idleclean              : 1;
+     unsigned long wait_host_idleclean            : 1;
+     unsigned long wait_extern_sig                : 1;
+     unsigned long cmdfifo_entries                : 7;
+     unsigned long                                : 3;
+     unsigned long wait_both_crtc_pflip           : 1;
+     unsigned long eng_display_select             : 1;
+     } wait_until_t;
+
+typedef union {
+     unsigned long val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+typedef struct _isync_cntl_t {
+     unsigned long isync_any2d_idle3d             : 1;
+     unsigned long isync_any3d_idle2d             : 1;
+     unsigned long isync_trig2d_idle3d            : 1;
+     unsigned long isync_trig3d_idle2d            : 1;
+     unsigned long isync_wait_idlegui             : 1;
+     unsigned long isync_cpscratch_idlegui        : 1;
+     unsigned long                                : 26;
+     } isync_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     isync_cntl_t f;
+} isync_cntl_u;
+
+typedef struct _rbbm_guicntl_t {
+     unsigned long host_data_swap                 : 2;
+     unsigned long                                : 30;
+     } rbbm_guicntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_guicntl_t f;
+} rbbm_guicntl_u;
+
+typedef struct _rbbm_status_t {
+     unsigned long cmdfifo_avail                  : 7;
+     unsigned long                                : 1;
+     unsigned long hirq_on_rbb                    : 1;
+     unsigned long cprq_on_rbb                    : 1;
+     unsigned long cfrq_on_rbb                    : 1;
+     unsigned long hirq_in_rtbuf                  : 1;
+     unsigned long cprq_in_rtbuf                  : 1;
+     unsigned long cfrq_in_rtbuf                  : 1;
+     unsigned long cf_pipe_busy                   : 1;
+     unsigned long eng_ev_busy                    : 1;
+     unsigned long cp_cmdstrm_busy                : 1;
+     unsigned long e2_busy                        : 1;
+     unsigned long rb2d_busy                      : 1;
+     unsigned long rb3d_busy                      : 1;
+     unsigned long se_busy                        : 1;
+     unsigned long re_busy                        : 1;
+     unsigned long tam_busy                       : 1;
+     unsigned long tdm_busy                       : 1;
+     unsigned long pb_busy                        : 1;
+     unsigned long                                : 6;
+     unsigned long gui_active                     : 1;
+     } rbbm_status_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+typedef struct _rbbm_cntl_t {
+     unsigned long rb_settle                      : 4;
+     unsigned long abortclks_hi                   : 3;
+     unsigned long                                : 1;
+     unsigned long abortclks_cp                   : 3;
+     unsigned long                                : 1;
+     unsigned long abortclks_cfifo                : 3;
+     unsigned long                                : 2;
+     unsigned long cpq_data_swap                  : 1;
+     unsigned long                                : 3;
+     unsigned long no_abort_idct                  : 1;
+     unsigned long no_abort_bios                  : 1;
+     unsigned long no_abort_fb                    : 1;
+     unsigned long no_abort_cp                    : 1;
+     unsigned long no_abort_hi                    : 1;
+     unsigned long no_abort_hdp                   : 1;
+     unsigned long no_abort_mc                    : 1;
+     unsigned long no_abort_aic                   : 1;
+     unsigned long no_abort_vip                   : 1;
+     unsigned long no_abort_disp                  : 1;
+     unsigned long no_abort_cg                    : 1;
+     } rbbm_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+typedef struct _rbbm_soft_reset_t {
+     unsigned long soft_reset_cp                  : 1;
+     unsigned long soft_reset_hi                  : 1;
+     unsigned long reserved3                      : 3;
+     unsigned long soft_reset_e2                  : 1;
+     unsigned long reserved2                      : 2;
+     unsigned long soft_reset_mc                  : 1;
+     unsigned long reserved1                      : 2;
+     unsigned long soft_reset_disp                : 1;
+     unsigned long soft_reset_cg                  : 1;
+     unsigned long                                : 19;
+     } rbbm_soft_reset_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+typedef struct _nqwait_until_t {
+     unsigned long wait_gui_idle                  : 1;
+     unsigned long                                : 31;
+     } nqwait_until_t;
+
+typedef union {
+     unsigned long val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+typedef struct _rbbm_debug_t {
+     unsigned long rbbm_debug                     : 32;
+     } rbbm_debug_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+typedef struct _rbbm_cmdfifo_addr_t {
+     unsigned long cmdfifo_addr                   : 6;
+     unsigned long                                : 26;
+     } rbbm_cmdfifo_addr_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_cmdfifo_addr_t f;
+} rbbm_cmdfifo_addr_u;
+
+typedef struct _rbbm_cmdfifo_datal_t {
+     unsigned long cmdfifo_datal                  : 32;
+     } rbbm_cmdfifo_datal_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_cmdfifo_datal_t f;
+} rbbm_cmdfifo_datal_u;
+
+typedef struct _rbbm_cmdfifo_datah_t {
+     unsigned long cmdfifo_datah                  : 12;
+     unsigned long                                : 20;
+     } rbbm_cmdfifo_datah_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_cmdfifo_datah_t f;
+} rbbm_cmdfifo_datah_u;
+
+typedef struct _rbbm_cmdfifo_stat_t {
+     unsigned long cmdfifo_rptr                   : 6;
+     unsigned long                                : 2;
+     unsigned long cmdfifo_wptr                   : 6;
+     unsigned long                                : 18;
+     } rbbm_cmdfifo_stat_t;
+
+typedef union {
+     unsigned long val : 32;
+     rbbm_cmdfifo_stat_t f;
+} rbbm_cmdfifo_stat_u;
+
+typedef struct _clk_pin_cntl_t {
+     unsigned long osc_en                         : 1;
+     unsigned long osc_gain                       : 5;
+     unsigned long dont_use_xtalin                : 1;
+     unsigned long xtalin_pm_en                   : 1;
+     unsigned long xtalin_dbl_en                  : 1;
+     unsigned long                                : 7;
+     unsigned long cg_debug                       : 16;
+     } clk_pin_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     clk_pin_cntl_t f;
+} clk_pin_cntl_u;
+
+typedef struct _pll_ref_fb_div_t {
+     unsigned long pll_ref_div                    : 4;
+     unsigned long                                : 4;
+     unsigned long pll_fb_div_int                 : 6;
+     unsigned long                                : 2;
+     unsigned long pll_fb_div_frac                : 3;
+     unsigned long                                : 1;
+     unsigned long pll_reset_time                 : 4;
+     unsigned long pll_lock_time                  : 8;
+     } pll_ref_fb_div_t;
+
+typedef union {
+     unsigned long val : 32;
+     pll_ref_fb_div_t f;
+} pll_ref_fb_div_u;
+
+typedef struct _pll_cntl_t {
+     unsigned long pll_pwdn                       : 1;
+     unsigned long pll_reset                      : 1;
+     unsigned long pll_pm_en                      : 1;
+     unsigned long pll_mode                       : 1;
+     unsigned long pll_refclk_sel                 : 1;
+     unsigned long pll_fbclk_sel                  : 1;
+     unsigned long pll_tcpoff                     : 1;
+     unsigned long pll_pcp                        : 3;
+     unsigned long pll_pvg                        : 3;
+     unsigned long pll_vcofr                      : 1;
+     unsigned long pll_ioffset                    : 2;
+     unsigned long pll_pecc_mode                  : 2;
+     unsigned long pll_pecc_scon                  : 2;
+     unsigned long pll_dactal                     : 4;
+     unsigned long pll_cp_clip                    : 2;
+     unsigned long pll_conf                       : 3;
+     unsigned long pll_mbctrl                     : 2;
+     unsigned long pll_ring_off                   : 1;
+     } pll_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     pll_cntl_t f;
+} pll_cntl_u;
+
+typedef struct _sclk_cntl_t {
+     unsigned long sclk_src_sel                   : 2;
+     unsigned long                                : 2;
+     unsigned long sclk_post_div_fast             : 4;
+     unsigned long sclk_clkon_hys                 : 3;
+     unsigned long sclk_post_div_slow             : 4;
+     unsigned long disp_cg_ok2switch_en           : 1;
+     unsigned long sclk_force_reg                 : 1;
+     unsigned long sclk_force_disp                : 1;
+     unsigned long sclk_force_mc                  : 1;
+     unsigned long sclk_force_extmc               : 1;
+     unsigned long sclk_force_cp                  : 1;
+     unsigned long sclk_force_e2                  : 1;
+     unsigned long sclk_force_e3                  : 1;
+     unsigned long sclk_force_idct                : 1;
+     unsigned long sclk_force_bist                : 1;
+     unsigned long busy_extend_cp                 : 1;
+     unsigned long busy_extend_e2                 : 1;
+     unsigned long busy_extend_e3                 : 1;
+     unsigned long busy_extend_idct               : 1;
+     unsigned long                                : 3;
+     } sclk_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     sclk_cntl_t f;
+} sclk_cntl_u;
+
+typedef struct _pclk_cntl_t {
+     unsigned long pclk_src_sel                   : 2;
+     unsigned long                                : 2;
+     unsigned long pclk_post_div                  : 4;
+     unsigned long                                : 8;
+     unsigned long pclk_force_disp                : 1;
+     unsigned long                                : 15;
+     } pclk_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     pclk_cntl_t f;
+} pclk_cntl_u;
+
+typedef struct _clk_test_cntl_t {
+     unsigned long testclk_sel                    : 4;
+     unsigned long                                : 3;
+     unsigned long start_check_freq               : 1;
+     unsigned long tstcount_rst                   : 1;
+     unsigned long                                : 15;
+     unsigned long test_count                     : 8;
+     } clk_test_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     clk_test_cntl_t f;
+} clk_test_cntl_u;
+
+typedef struct _pwrmgt_cntl_t {
+     unsigned long pwm_enable                     : 1;
+     unsigned long                                : 1;
+     unsigned long pwm_mode_req                   : 2;
+     unsigned long pwm_wakeup_cond                : 2;
+     unsigned long pwm_fast_noml_hw_en            : 1;
+     unsigned long pwm_noml_fast_hw_en            : 1;
+     unsigned long pwm_fast_noml_cond             : 4;
+     unsigned long pwm_noml_fast_cond             : 4;
+     unsigned long pwm_idle_timer                 : 8;
+     unsigned long pwm_busy_timer                 : 8;
+     } pwrmgt_cntl_t;
+
+typedef union {
+     unsigned long val : 32;
+     pwrmgt_cntl_t f;
+} pwrmgt_cntl_u;
+
+typedef struct _pwrmgt_status_t {
+     unsigned long pwm_mode                       : 2;
+     unsigned long                                : 30;
+     } pwrmgt_status_t;
+
+typedef union {
+     unsigned long val : 32;
+     pwrmgt_status_t f;
+} pwrmgt_status_u;
+
+typedef struct tagDISPLAYSTATE {
+lcd_format_u	       LcdFormat;
+crtc_total_u	       CrtcTotal;
+active_h_disp_u	       ActiveHDisp;
+active_v_disp_u	       ActiveVDisp;
+crtc_ss_u	       CrtcSS;
+crtc_ls_u	       CrtcLS;
+crtc_gs_u	       CrtcGS;
+crtc_vpos_gs_u	       CrtcVPosGS;
+crtc_gclk_u	       CrtcGClk;
+crtc_goe_u	       CrtcGOE;
+crtc_rev_u	       CrtcRev;
+crtc_dclk_u	       CrtcDClk;
+crtc_default_count_u   CrtcDefaultCount;
+crtc_frame_u	       CrtcFrame;
+crtc_frame_vpos_u      CrtcFrameVPos;
+lcdd_cntl1_u	       LcddCntl1;
+lcdd_cntl2_u	       LcddCntl2;
+genlcd_cntl1_u	       GenlcdCntl1;
+genlcd_cntl2_u	       GenlcdCntl2;
+lcd_background_color_u LcdBackgroundColor;
+brightness_cntl_u      Brightness_Cntl;
+} DISPLAYSTATE;
+
+typedef struct {
+s16		X_Top_Left;      	// x coordinate of top left corner
+s16		Y_Top_Left;	   	// y coordinate of top left corner
+s16		X_Bottom_Right;		// x coordinate of bottom right corner
+s16		Y_Bottom_Right;		// y coordinate of bottom right corner
+} ATI_CLIPRECT;
+
+typedef struct tagGUISTATE {
+dp_cntl_u            DpCntl;
+dp_gui_master_cntl_u GMC;
+e2_arithmetic_cntl_u E2AC;
+global_alpha_u	     GlobalAlpha;
+dst_pitch_u          dstPitch;
+dst_offset_u         dstOffset;
+src_pitch_u          srcPitch;
+src_offset_u         srcOffset;
+u32		     FrgrdColour;
+u32		     BkgrdColour;
+ATI_CLIPRECT	     SrcClipRect;
+ATI_CLIPRECT	     DstClipRect;
+u32 		     BrushOffset;
+u16		     BrushHandle;
+// for 16bpp, SRC must be the same type as DST, can't go from 1555->565
+s8                   TurnOnDst565ForNon2D; 
+} GUISTATE;
+
+typedef struct tagGFXWINSTATE {
+graphic_ctrl_u		GraphicCtrl;
+graphic_offset_u        GraphicOffset;
+graphic_pitch_u		GraphicPitch;   // byte-based
+graphic_h_disp_u	GraphicHDisp;
+graphic_v_disp_u	GraphicVDisp;
+s8                      TurnOnDisp565;
+// These memory offsets need to be translated before writing to registers
+u32                     Grp_Offset;
+u32			Grp_W;
+u32			Grp_H;
+u32			Grp_Src_X;
+u32			Grp_Src_Y;
+u32			Grp_Src_W;      // pixel-based
+} GFXWINSTATE;
+
+typedef struct tagPREVSTATE {
+u16              PrevOverlayX;
+u16              PrevOverlayY;
+u8               bOverlayWasOn;
+u16              PrevGfxWinX;
+u16              PrevGfxWinY;
+u8               bGfxWinWasOn;
+} PREVSTATE;
+
+typedef struct tagPOWERSTATE {
+clk_pin_cntl_u   ClkPinCntl;
+pll_ref_fb_div_u PllRefFbDiv;
+pll_cntl_u       PllCntl;
+sclk_cntl_u      SclkCntl;
+pclk_cntl_u      PclkCntl;
+clk_test_cntl_u  ClkTestCntl;
+pwrmgt_cntl_u    PwrmgtCntl;
+u32              Freq;
+u8               tf100;
+u8		 tf80;
+u8               tf20;
+u8               M;
+u8               N_int;
+u8               N_fac;
+u8               lock_time;
+u8               tfgoal;
+u8               AutoMode;
+u8               PWMMode;
+u16              FastSclk;
+u16              NormSclk;
+PREVSTATE        PrevState;
+} POWERSTATE;
+
+typedef struct tagAPERTURE {
+u32 MMRegBase;
+u32 CfgRegBase;
+u32 McFbStart;
+u32 McFbTop;
+u32 McExtMemStart;
+u32 McExtMemTop;
+u32 WrapStart;
+u32 WrapTop;
+} APERTURE;
+
+#endif
+
--- /dev/null
+++ linux-2.6.10-rc1/include/video/corgi_backlight.h
@@ -0,0 +1,35 @@
+/*
+ *
+ * (C) Copyright 2002 Lineo Japan, Inc.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on include/video/sa1100_frontlight.h
+ * 
+ * ChangeLog:
+ *    06-Nov-2002 SHARP for SL-B500/5600
+ */
+
+#ifndef __CORGI_FRONTLIGHT_H
+#define __CORGI_FRONTLIGHT_H
+
+#define CORGI_BL_IOCTL_ON		1
+#define CORGI_BL_IOCTL_OFF		2
+#define CORGI_BL_IOCTL_STEP_CONTRAST	  100
+#define CORGI_BL_IOCTL_GET_STEP_CONTRAST 101
+#define CORGI_BL_IOCTL_GET_STEP          102
+
+#define CORGI_BL_RESET_CONTRAST		(-1)
+#define CORGI_BL_CAUTION_CONTRAST	(3)
+
+#define BL_MAJOR  254
+#define BL_NAME   "corgi-bl"
+
+void corgibl_blank(int blank);
+int corgibl_pm_callback(struct pm_dev* pm_dev, pm_request_t req, void *data);
+void corgibl_temporary_contrast_set(void);
+void corgibl_temporary_contrast_reset(void);
+void corgibl_set_limit_contrast(int val);
+
+#endif /*  __CORGI_FRONTLIGHT_H  */