diff -uNr linux-2.6.7-1/arch/arm/Kconfig linux-2.6.7/arch/arm/Kconfig --- linux-2.6.7-1/arch/arm/Kconfig 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/arch/arm/Kconfig 2004-06-21 12:32:49.000000000 +0100 @@ -544,7 +544,7 @@ config LEDS bool "Timer and CPU usage LEDs" - depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB || MACH_POODLE + depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB || MACH_POODLE || MACH_HUSKY help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. @@ -558,7 +558,7 @@ config LEDS_TIMER bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || MACH_MAINSTONE || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE_PB || MACH_POODLE) - depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB || MACH_POODLE + depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB || MACH_POODLE || MACH_HUSKY default y if ARCH_EBSA110 help If you say Y here, one of the system LEDs (the green one on the @@ -573,7 +573,7 @@ config LEDS_CPU bool "CPU usage LED" - depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE_PB || MACH_POODLE) + depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE_PB || MACH_POODLE || MACH_HUSKY) help If you say Y here, the red LED will be used to give a good real time indication of CPU usage, by lighting whenever the idle task diff -uNr linux-2.6.7-1/arch/arm/boot/compressed/head-xscale.S linux-2.6.7/arch/arm/boot/compressed/head-xscale.S --- linux-2.6.7-1/arch/arm/boot/compressed/head-xscale.S 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/arch/arm/boot/compressed/head-xscale.S 2004-06-21 12:32:49.000000000 +0100 @@ -52,6 +52,18 @@ mov r7, #MACH_TYPE_POODLE #endif +#ifdef CONFIG_MACH_CORGI + mov r7, MACH_TYPE_CORGI +@ mov r7, #0xa7 +@ add r7, r7, #0x100 +#endif + +#ifdef CONFIG_MACH_HUSKY +@ mov r7, #MACH_TYPE_HUSKY + mov r7, #0x1f + add r7, r7, #0x200 +#endif + #ifdef CONFIG_ARCH_IQ80310 /* * Crank the CPU up to 733MHz diff -uNr linux-2.6.7-1/arch/arm/boot/compressed/head.S linux-2.6.7/arch/arm/boot/compressed/head.S --- linux-2.6.7-1/arch/arm/boot/compressed/head.S 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/arch/arm/boot/compressed/head.S 2004-06-21 12:32:49.000000000 +0100 @@ -365,11 +365,19 @@ mov r8, r0, lsr #18 mov r8, r8, lsl #18 @ start of RAM add r9, r8, #0x10000000 @ a reasonable RAM size - mov r1, #0x12 +@#ifdef CONFIG_CPU_XSCALE + mov r1, #0x02 +@#else +@ mov r1, #0x12 +@#endif orr r1, r1, #3 << 10 add r2, r3, #16384 1: cmp r1, r8 @ if virt > start of RAM - orrhs r1, r1, #0x0c @ set cacheable, bufferable +@#ifdef CONFIG_XSCALE_CACHE_ERRATA + orrhs r1, r1, #0x08 @ set cacheable, not bufferable +@#else +@ orrhs r1, r1, #0x0c @ set cacheable, bufferable +@#endif cmp r1, r9 @ if virt > end of RAM bichs r1, r1, #0x0c @ clear cacheable, bufferable str r1, [r0], #4 @ 1:1 mapping diff -uNr linux-2.6.7-1/arch/arm/mach-pxa/Kconfig linux-2.6.7/arch/arm/mach-pxa/Kconfig --- linux-2.6.7-1/arch/arm/mach-pxa/Kconfig 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/arch/arm/mach-pxa/Kconfig 2004-06-21 12:32:49.000000000 +0100 @@ -22,10 +22,23 @@ bool "SHARP Poodle" select PXA25x +config MACH_CORGI + bool "SHARP Corgi (SL-C700)" + select PXA25x + +config MACH_SHEPHERD + bool "SHARP Shepherd (SL-C750)" + select PXA25x + +config MACH_HUSKY + bool "SHARP Husky (SL-C760)" + select PXA25x + config SHARP_LOCOMO bool "SHARP LoCoMo support" default Y - depends MACH_POODLE + depends MACH_POODLE || MACH_CORGI || MACH_HUSKY + endchoice diff -uNr linux-2.6.7-1/arch/arm/mach-pxa/Makefile linux-2.6.7/arch/arm/mach-pxa/Makefile --- linux-2.6.7-1/arch/arm/mach-pxa/Makefile 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/arch/arm/mach-pxa/Makefile 2004-06-21 12:32:49.000000000 +0100 @@ -12,6 +12,9 @@ obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_MACH_POODLE) += poodle.o +obj-$(CONFIG_MACH_CORGI) += corgi.o +obj-$(CONFIG_MACH_SHEPHERD) += corgi.o +obj-$(CONFIG_MACH_HUSKY) += corgi.o pxa_ssp.o # Support for blinky lights led-y := leds.o @@ -19,6 +22,9 @@ led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o led-$(CONFIG_MACH_POODLE) += leds-poodle.o +led-$(CONFIG_MACH_CORGI) += leds-corgi.o +led-$(CONFIG_MACH_SHEPHERD) += leds-corgi.o +led-$(CONFIG_MACH_HUSKY) += leds-corgi.o obj-$(CONFIG_LEDS) += $(led-y) diff -uNr linux-2.6.7-1/arch/arm/mach-pxa/corgi.c linux-2.6.7/arch/arm/mach-pxa/corgi.c --- linux-2.6.7-1/arch/arm/mach-pxa/corgi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.7/arch/arm/mach-pxa/corgi.c 2004-06-21 12:32:49.000000000 +0100 @@ -0,0 +1,245 @@ +/* + * linux/arch/arm/mach-pxa/corgi.c + * + * Support for the SHARP Corgi Board. + * + * Copyright: Lineo Japan Inc. + * + * Based on: + * linux/arch/arm/mach-pxa/lubbock.c + * + * Support for the Intel DBPXA250 Development Platform. + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Change Log + * 12-Dec-2002 Sharp Corporation for Corgi + * 01-Apr-2003 Sharp for Shepherd + * + * Mar 10, 2004: Lots of changes to port to 2.6 by John Lenz + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + +extern void pxa_ssp_init(void); + +static void __init scoop_init(void) +{ + +#define CORGI_SCP_INIT_DATA(adr,dat) (((adr)<<16)|(dat)) +#define CORGI_SCP_INIT_DATA_END ((unsigned long)-1) + static const unsigned long scp_init[] = + { + CORGI_SCP_INIT_DATA(CORGI_SCP_MCR,0x0140), // 00 + CORGI_SCP_INIT_DATA(CORGI_SCP_MCR,0x0100), + CORGI_SCP_INIT_DATA(CORGI_SCP_CDR,0x0000), // 04 + CORGI_SCP_INIT_DATA(CORGI_SCP_CPR,0x0000), // 0C + CORGI_SCP_INIT_DATA(CORGI_SCP_CCR,0x0000), // 10 + CORGI_SCP_INIT_DATA(CORGI_SCP_IMR,0x0000), // 18 + CORGI_SCP_INIT_DATA(CORGI_SCP_IRM,0x00FF), // 14 + CORGI_SCP_INIT_DATA(CORGI_SCP_ISR,0x0000), // 1C + CORGI_SCP_INIT_DATA(CORGI_SCP_IRM,0x0000), + CORGI_SCP_INIT_DATA(CORGI_SCP_GPCR,CORGI_SCP_IO_DIR), // 20 + CORGI_SCP_INIT_DATA(CORGI_SCP_GPWR,CORGI_SCP_IO_OUT), // 24 + CORGI_SCP_INIT_DATA_END + }; + int i; + for(i=0; scp_init[i] != CORGI_SCP_INIT_DATA_END; i++) + { + int adr = scp_init[i] >> 16; + CORGI_SCP_REG(adr) = scp_init[i] & 0xFFFF; + } +} + +static spinlock_t scoop_lock = SPIN_LOCK_UNLOCKED; + +unsigned short set_scoop_gpio(unsigned short bit) +{ + unsigned short gpio_bit; + unsigned long flag; + + spin_lock_irqsave(&scoop_lock, flag); + gpio_bit = CORGI_SCP_REG_GPWR | bit; + CORGI_SCP_REG_GPWR = gpio_bit; + spin_unlock_irqrestore(&scoop_lock, flag); + + return gpio_bit; +} + +unsigned short reset_scoop_gpio(unsigned short bit) +{ + unsigned short gpio_bit; + unsigned long flag; + + spin_lock_irqsave(&scoop_lock, flag); + gpio_bit = CORGI_SCP_REG_GPWR & ~bit; + CORGI_SCP_REG_GPWR = gpio_bit; + spin_unlock_irqrestore(&scoop_lock, flag); + + return gpio_bit; +} + +static void __init corgi_init_irq(void) +{ + pxa_init_irq(); + + /* setup extra corgi irqs */ + + /* i2c initialize */ + //i2c_init(); RPP Fixme! + + /* scoop initialize */ + scoop_init(); + + /* initialize SSP & CS */ + pxa_ssp_init(); +} + +sharpsl_flash_param_info sharpsl_flash_param; + +void sharpsl_get_param(void) +{ + // get comadj + sharpsl_flash_param.comadj_keyword = (unsigned int) FLASH_DATA(FLASH_COMADJ_MAGIC_ADR); + sharpsl_flash_param.comadj = (unsigned int) FLASH_DATA(FLASH_COMADJ_DATA_ADR); + + // get phad + sharpsl_flash_param.phad_keyword = (unsigned int) FLASH_DATA(FLASH_PHAD_MAGIC_ADR); + sharpsl_flash_param.phadadj = (unsigned int) FLASH_DATA(FLASH_PHAD_DATA_ADR); +} + +int sharpsl_get_comadj() +{ + if ( sharpsl_flash_param.comadj_keyword == FLASH_COMADJ_MAJIC ) { + return sharpsl_flash_param.comadj; + } else { + return -1; + } +} + +int sharpsl_get_phadadj() +{ + if ( sharpsl_flash_param.phad_keyword == FLASH_PHAD_MAJIC ) { + return sharpsl_flash_param.phadadj; + } else { + return -1; + } + } + +/*EXPORT_SYMBOL(sharpsl_get_phadaj); +EXPORT_SYMBOL(sharpsl_get_comadj);*/ + +#if 0 +static void __init +fixup_corgi(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ +#if defined(CONFIG_MACH_SHEPHERD) || defined(CONFIG_MACH_HUSKY) + SET_BANK (0, 0xa0000000, 64*1024*1024); +#else + SET_BANK (0, 0xa0000000, 32*1024*1024); +#endif + mi->nr_banks = 1; +#if defined(CONFIG_BLK_DEV_INITRD) + setup_ramdisk (1, 0, 0, 8192); + setup_initrd (__phys_to_virt(0xa1000000), 4*1024*1024); + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0); +#elif defined(CONFIG_MTD) + ROOT_DEV = MKDEV(31, 0); /* /dev/mtdblock0 */ +#endif + +#ifdef CONFIG_SHARPSL_BOOTLDR_PARAMS + if (params->u1.s.page_size != PAGE_SIZE) { + params->u1.s.page_size = PAGE_SIZE; + params->u1.s.nr_pages = 32 * 1024 * 1024 / PAGE_SIZE; + params->u1.s.ramdisk_size = 0; + params->u1.s.flags = FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT; + params->u1.s.rootdev = ROOT_DEV; + params->u1.s.initrd_start = 0; + params->u1.s.initrd_size = 0; + params->u1.s.rd_start = 0; + params->u1.s.system_rev = 0; + params->u1.s.system_serial_low = 0; + params->u1.s.system_serial_high = 0; + strcpy(params->commandline, CONFIG_CMDLINE); + } + + //sharpsl_get_param(); + +#endif +} +#endif + +static struct map_desc corgi_io_desc[] __initdata = { + /* virtual physical length */ + { 0xf1000000, 0x08000000, 0x01000000, MT_DEVICE }, /* LCDC (readable for Qt driver) */ + { 0xf2000000, 0x10800000, 0x00001000, MT_DEVICE }, /* SCOOP */ + { 0xf2100000, 0x0C000000, 0x00001000, MT_DEVICE }, /* Nand Flash */ + { 0xef000000, 0x00000000, 0x00800000, MT_DEVICE }, /* Boot Flash */ +}; + +static void __init corgi_map_io(void) +{ + pxa_map_io(); + iotable_init(corgi_io_desc,ARRAY_SIZE(corgi_io_desc)); + +#if 0 + /* This enables the BTUART */ + CKEN |= CKEN7_BTUART; + set_GPIO_mode(GPIO42_BTRXD_MD); + set_GPIO_mode(GPIO43_BTTXD_MD); + set_GPIO_mode(GPIO44_BTCTS_MD); + set_GPIO_mode(GPIO45_BTRTS_MD); +#endif + + /* setup sleep mode values */ + PWER = 0x00000002; + PFER = 0x00000000; + PRER = 0x00000002; + PGSR0 = 0x0158C000; + PGSR1 = 0x00FF0080; + PGSR2 = 0x0001C004; + PCFR |= PCFR_OPDE; +} + +#if defined(CONFIG_MACH_HUSKY) +MACHINE_START(HUSKY, "SHARP Husky") +#elif defined(CONFIG_MACH_SHEPHERD) +MACHINE_START(SHEPHERD, "SHARP Shepherd") +#else +MACHINE_START(CORGI, "SHARP Corgi") +#endif + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000)) +#ifdef CONFIG_SHARPSL_BOOTLDR_PARAMS + BOOT_PARAMS(0xa0000100) +#endif +/* FIXUP(fixup_corgi)*/ + MAPIO(corgi_map_io) + INITIRQ(corgi_init_irq) +MACHINE_END diff -uNr linux-2.6.7-1/arch/arm/mach-pxa/leds-corgi.c linux-2.6.7/arch/arm/mach-pxa/leds-corgi.c --- linux-2.6.7-1/arch/arm/mach-pxa/leds-corgi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.7/arch/arm/mach-pxa/leds-corgi.c 2004-06-21 12:32:49.000000000 +0100 @@ -0,0 +1,135 @@ +/* + * linux/arch/arm/mach-pxa/leds-corgi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copied from arch/arm/mach-sa1100/leds-collie.c + * ChangeLog: + * - John Lenz <4/27/04> - added support for new locomo device model + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include "leds.h" + +#define LED_STATE_ENABLED 1 +#define LED_STATE_CLAIMED 2 + +static struct locomo_dev *locomo_dev = NULL; +static unsigned int led_state; +static unsigned int hw_led0_state = 0; +static unsigned int hw_led1_state = 0; + +#define LED_ONOFF_MASK (LOCOMO_LPT_TOFL|LOCOMO_LPT_TOFH) +#define LED_OFF(REG) ((REG)|=LOCOMO_LPT_TOFL) +#define LED_ON(REG) ((REG)=((REG)&~LED_ONOFF_MASK)|LOCOMO_LPT_TOFH) +#define LED_FLIP(REG) ((REG)^=LED_ONOFF_MASK) + +void corgi_leds_event(led_event_t evt) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (evt) { + case led_start: + led_state = LED_STATE_ENABLED; + LED_ON(hw_led0_state); + LED_ON(hw_led1_state); + break; + + case led_stop: + led_state &= ~LED_STATE_ENABLED; + break; + + case led_claim: + led_state |= LED_STATE_CLAIMED; + LED_ON(hw_led0_state); + LED_ON(hw_led1_state); + break; + + case led_release: + led_state &= ~LED_STATE_CLAIMED; + LED_ON(hw_led0_state); + LED_ON(hw_led1_state); + break; + +#ifdef CONFIG_LEDS_TIMER + case led_timer: + if (!(led_state & LED_STATE_CLAIMED)) { + LED_FLIP(hw_led0_state); + } + break; +#endif + +#ifdef CONFIG_LEDS_CPU + case led_idle_start: + /* LED off when system is idle */ + if (!(led_state & LED_STATE_CLAIMED)) + LED_OFF(hw_led1_state); + break; + + case led_idle_end: + if (!(led_state & LED_STATE_CLAIMED)) + LED_ON(hw_led1_state); + break; +#endif + + default: + break; + } + + + if (locomo_dev && led_state & LED_STATE_ENABLED) { + locomo_writel(hw_led0_state, locomo_dev->mapbase + LOCOMO_LPT0); + locomo_writel(hw_led1_state, locomo_dev->mapbase + LOCOMO_LPT1); + } + + local_irq_restore(flags); +} + +static int corgiled_probe(struct locomo_dev *dev) { + /* set up the initial led states, since due to the init order, + * corgi_leds_event(led_start) might have been called before this */ + /*if (led_state & LED_STATE_ENABLED) { + //LCM_LPT0 = hw_led0_state; + locomo_writel(hw_led0_state, dev->mapbase + LOCOMO_LPT0); + //LCM_LPT1 = hw_led1_state; + locomo_writel(hw_led1_state, dev->mapbase + LOCOMO_LPT1); + }*/ + locomo_dev = dev; + return 0; +} + +static int corgiled_remove(struct locomo_dev *dev) { + locomo_dev = NULL; + return 0; +} + +static struct locomo_driver corgiled_driver = { + .drv = { + .name = "locomoled" + }, + .devid = LOCOMO_DEVID_LED, + .probe = corgiled_probe, + .remove = corgiled_remove, +}; + +static int __init corgiled_init(void) { + return locomo_driver_register(&corgiled_driver); +} + +device_initcall(corgiled_init); + +MODULE_AUTHOR("John Lenz "); +MODULE_DESCRIPTION("LoCoMo Corgi LED driver"); +MODULE_LICENSE("GPL"); diff -uNr linux-2.6.7-1/arch/arm/mach-pxa/leds.c linux-2.6.7/arch/arm/mach-pxa/leds.c --- linux-2.6.7-1/arch/arm/mach-pxa/leds.c 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/arch/arm/mach-pxa/leds.c 2004-06-21 12:32:49.000000000 +0100 @@ -26,7 +26,8 @@ leds_event = idp_leds_event; if (machine_is_poodle()) leds_event = poodle_leds_event; - + if (machine_is_corgi()) + leds_event = corgi_leds_event; leds_event(led_start); return 0; } diff -uNr linux-2.6.7-1/arch/arm/mach-pxa/leds.h linux-2.6.7/arch/arm/mach-pxa/leds.h --- linux-2.6.7-1/arch/arm/mach-pxa/leds.h 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/arch/arm/mach-pxa/leds.h 2004-06-21 12:32:49.000000000 +0100 @@ -11,3 +11,4 @@ extern void lubbock_leds_event(led_event_t evt); extern void mainstone_leds_event(led_event_t evt); extern void poodle_leds_event(led_event_t evt); +extern void corgi_leds_event(led_event_t evt); diff -uNr linux-2.6.7-1/arch/arm/mach-pxa/pxa_ssp.c linux-2.6.7/arch/arm/mach-pxa/pxa_ssp.c --- linux-2.6.7-1/arch/arm/mach-pxa/pxa_ssp.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.7/arch/arm/mach-pxa/pxa_ssp.c 2004-06-21 12:32:49.000000000 +0100 @@ -0,0 +1,243 @@ +/* + * linux/arch/arm/mach-pxa/pxa_ssp.c + * + * SSP read routines for discovery/poodle/corgi (SHARP) + * + * Copyright (C) 2002 LINEO Japan, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Change Log + * 12-Dec-2002 Sharp Corporation for Poodle and Corgi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#if defined(CONFIG_MACH_CORGI) || defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD) +#include +#include +#include +#endif + +static spinlock_t pxa_ssp_lock = SPIN_LOCK_UNLOCKED; +static unsigned long flag; + +unsigned long ssp_get_dac_val(ulong data, int cs) +{ + unsigned long ret; + + spin_lock_irqsave(&pxa_ssp_lock, flag); + +#if defined(CONFIG_MACH_CORGI) || defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD) + switch (cs) { +#if 0 + case CS_MAX1111: + disable_irq(IRQ_GPIO_TP_INT); + SSCR0 = 0x387; + GPSR0 = GPIO_bit(GPIO19_DREQ1); /* TG */ + GPCR0 = GPIO_bit(GPIO20_DREQ0); /* MAX1111 */ + GPSR0 = GPIO_bit(GPIO24_SFRM); /* ADS7846 */ + break; +#endif + case CS_ADS7846: + SSCR0 = 0xab; + GPSR0 = GPIO_bit(GPIO19_DREQ1); /* TG */ + GPSR0 = GPIO_bit(GPIO20_DREQ0); /* MAX1111 */ + GPCR0 = GPIO_bit(GPIO24_SFRM); /* ADS7846 */ + break; + default: + spin_unlock_irqrestore(&pxa_ssp_lock, flag); + return 0; + } +#endif + + SSDR = data; + while ((SSSR & SSSR_TNF_MSK) != SSSR_TNF_MSK); + udelay(1); + while ((SSSR & SSSR_RNE_MSK) != SSSR_RNE_MSK); + ret = (SSDR); + +#if defined(CONFIG_MACH_CORGI) || defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD) +#if 0 + if (cs == CS_MAX1111) { + GEDR(GPIO_TP_INT) = GPIO_bit(GPIO_TP_INT); + enable_irq(IRQ_GPIO_TP_INT); + } + SSCR0 = 0x1ab; +#endif +#endif + spin_unlock_irqrestore(&pxa_ssp_lock, flag); + return ret; +} + +#define TG_GPIO_GAFR0_MASK 0x000cc0c0 + +#if defined(CONFIG_MACH_CORGI) || defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD) +unsigned long ssp_put_dac_val(ulong data, int cs) +{ + unsigned long ret; + int on_value = 0, i; + + spin_lock_irqsave(&pxa_ssp_lock, flag); + + switch (cs) { + case CS_ADS7846: + SSCR0 = 0xab; + GPSR0 = GPIO_bit(GPIO19_DREQ1); /* TG */ + GPSR0 = GPIO_bit(GPIO20_DREQ0); /* MAX1111 */ + GPCR0 = GPIO_bit(GPIO24_SFRM); /* ADS7846 */ + SSDR = data; + while ((SSSR & SSSR_TNF_MSK) != SSSR_TNF_MSK); + break; + case CS_LZ9JG18: + GPDR0 = (GPDR0 & ~GPIO_bit(GPIO26_SRXD))| + GPIO_bit(GPIO23_SCLK)|GPIO_bit(GPIO25_STXD); + GAFR0_U &= ~(TG_GPIO_GAFR0_MASK | 0x30300); + GPSR0 = GPIO_bit(20)|GPIO_bit(24); + GPCR0 = GPIO_bit(19)|GPIO_bit(23)|GPIO_bit(25)|GPIO_bit(26); + udelay(10); + for( i = 0; i < 8; i++){ + if(data&0x80) + GPSR0 = GPIO_bit(25); /* SDO=H */ + else + GPCR0 = GPIO_bit(25); /* SDO=L */ + udelay(10); + GPSR0 = GPIO_bit(23); /* SCK=H */ + udelay(10); + GPCR0 = GPIO_bit(23); /* SCK=L */ + udelay(10); + data <<= 1; + } + GPCR0 = GPIO_bit(25); /* SDO=L */ + GPSR0 = GPIO_bit(19); /* CSB=H */ + GAFR0_U = (GAFR0_U & ~TG_GPIO_GAFR0_MASK)|0x88000; + spin_unlock_irqrestore(&pxa_ssp_lock, flag); + break; + default: + spin_unlock_irqrestore(&pxa_ssp_lock, flag); + return 0; + } + return ret; +} + +unsigned long ssp_only_get_dac_val(int cs) +{ + unsigned long ret; + + switch (cs) { + case CS_ADS7846: + break; + default: + return 0; + } + while ((SSSR & SSSR_RNE_MSK) != SSSR_RNE_MSK); + ret = (SSDR); + + SSCR0 = 0x1ab; + + spin_unlock_irqrestore(&pxa_ssp_lock, flag); + return ret; +} +#endif + +void pxa_ssp_init(void) +{ + /* initialize SSP */ + CKEN |= CKEN3_SSP; +#if defined(CONFIG_MACH_POODLE) + SSCR0 = 0x11ab; +#else + SSCR0 = 0x1ab; +#endif + SSCR1 = 0; + +#if defined(CONFIG_MACH_CORGI) || defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD) + /* CS control disable all */ + GPDR0 |= GPIO_bit(GPIO19_DREQ1); /* output */ + GPSR0 = GPIO_bit(GPIO19_DREQ1); /* High */ + GPDR0 |= GPIO_bit(GPIO20_DREQ0); /* output */ + GPSR0 = GPIO_bit(GPIO20_DREQ0); /* High */ + GPDR0 |= GPIO_bit(GPIO24_SFRM); /* output */ + GPSR0 = GPIO_bit(GPIO24_SFRM); /* High */ +#endif +} + +#if defined(CONFIG_MACH_CORGI) || defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD) +int ssp_get_max1111_val(ulong data) +{ + unsigned long ret; + volatile unsigned int dummy; + int voltage,voltage1,voltage2; + + spin_lock_irqsave(&pxa_ssp_lock, flag); + +// + SSCR0 = 0x387; + GPSR0 = GPIO_bit(GPIO19_DREQ1); /* TG */ + GPCR0 = GPIO_bit(GPIO20_DREQ0); /* MAX1111 */ + GPSR0 = GPIO_bit(GPIO24_SFRM); /* ADS7846 */ + + udelay(1); + +// TB1/RB1 + SSDR = data; + while ((SSSR & SSSR_TNF_MSK) != SSSR_TNF_MSK); + udelay(1); + while ((SSSR & SSSR_RNE_MSK) != SSSR_RNE_MSK); + dummy = SSDR; + +// TB12/RB2 + SSDR = 0; + while ((SSSR & SSSR_TNF_MSK) != SSSR_TNF_MSK); + udelay(1); + while ((SSSR & SSSR_RNE_MSK) != SSSR_RNE_MSK); + voltage1 = SSDR; + +// TB13/RB3 + SSDR = 0; + while ((SSSR & SSSR_TNF_MSK) != SSSR_TNF_MSK); + udelay(1); + while ((SSSR & SSSR_RNE_MSK) != SSSR_RNE_MSK); + voltage2 = SSDR; + +// + GPSR0 = GPIO_bit(GPIO19_DREQ1); /* TG */ + GPSR0 = GPIO_bit(GPIO20_DREQ0); /* MAX1111 */ + GPSR0 = GPIO_bit(GPIO24_SFRM); /* ADS7846 */ + SSCR0 = 0; + +// + if (voltage1 & 0xc0 || voltage2 & 0x3f){ + voltage = -1; + }else{ + voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03); + } + +// + spin_unlock_irqrestore(&pxa_ssp_lock, flag); + return voltage; +} +#endif + +#if defined(CONFIG_MACH_CORGI) || defined(CONFIG_MACH_HUSKY) || defined(CONFIG_MACH_SHEPHERD) +EXPORT_SYMBOL(ssp_get_max1111_val); +#endif +EXPORT_SYMBOL(ssp_get_dac_val); +EXPORT_SYMBOL(pxa_ssp_init); diff -uNr linux-2.6.7-1/arch/arm/tools/mach-types linux-2.6.7/arch/arm/tools/mach-types --- linux-2.6.7-1/arch/arm/tools/mach-types 2004-06-16 06:19:22.000000000 +0100 +++ linux-2.6.7/arch/arm/tools/mach-types 2004-06-21 12:32:49.000000000 +0100 @@ -546,3 +546,6 @@ skyminder MACH_SKYMINDER SKYMINDER 536 lpd79520 MACH_LPD79520 LPD79520 537 edb9302 MACH_EDB9302 EDB9302 538 +husky MACH_HUSKY HUSKY 543 +boxer MACH_BOXER BOXER 544 +shepherd MACH_SHEPHERD SHEPHERD 545 \ No newline at end of file diff -uNr linux-2.6.7-1/include/asm-arm/arch-pxa/corgi.h linux-2.6.7/include/asm-arm/arch-pxa/corgi.h --- linux-2.6.7-1/include/asm-arm/arch-pxa/corgi.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.7/include/asm-arm/arch-pxa/corgi.h 2004-06-21 12:32:49.000000000 +0100 @@ -0,0 +1,263 @@ +/* + * linux/include/asm-arm/arch-pxa/corgi.h + * + * (C) Copyright 2001 Lineo Japan, Inc. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Based on: + * + * linux/include/asm-arm/arch-sa1100/collie.h + * + * This file contains the hardware specific definitions for Collie + * + * (C) Copyright 2001 Lineo Japan, Inc. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * ChangeLog: + * 04-06-2001 Lineo Japan, Inc. + * 04-16-2001 SHARP Corporation + * + * Mar 10, 2004: Updates to 2.6 by John Lenz + */ +#ifndef __ASM_ARCH_CORGI_H +#define __ASM_ARCH_CORGI_H 1 + +/* + * LCDC internal I/O mappings + * + * We have the following mapping: + * phys virt + * 08000000 f1000000 + */ + + + +/* + * SCOOP internal I/O mappings + * + * We have the following mapping: + * phys virt + * 10800000 f2000000 + */ + + +#define CF_BUF_CTRL_BASE 0xF2000000 + +#define CORGI_SCP_REG(adr) (*(volatile unsigned short*)(CF_BUF_CTRL_BASE+(adr))) + +#define CORGI_SCP_MCR 0x00 +#define CORGI_SCP_CDR 0x04 +#define CORGI_SCP_CSR 0x08 +#define CORGI_SCP_CPR 0x0C +#define CORGI_SCP_CCR 0x10 +#define CORGI_SCP_IRR 0x14 +#define CORGI_SCP_IRM 0x14 +#define CORGI_SCP_IMR 0x18 +#define CORGI_SCP_ISR 0x1C +#define CORGI_SCP_GPCR 0x20 +#define CORGI_SCP_GPWR 0x24 +#define CORGI_SCP_GPRR 0x28 +#define CORGI_SCP_REG_MCR CORGI_SCP_REG(CORGI_SCP_MCR) +#define CORGI_SCP_REG_CDR CORGI_SCP_REG(CORGI_SCP_CDR) +#define CORGI_SCP_REG_CSR CORGI_SCP_REG(CORGI_SCP_CSR) +#define CORGI_SCP_REG_CPR CORGI_SCP_REG(CORGI_SCP_CPR) +#define CORGI_SCP_REG_CCR CORGI_SCP_REG(CORGI_SCP_CCR) +#define CORGI_SCP_REG_IRR CORGI_SCP_REG(CORGI_SCP_IRR) +#define CORGI_SCP_REG_IRM CORGI_SCP_REG(CORGI_SCP_IRM) +#define CORGI_SCP_REG_IMR CORGI_SCP_REG(CORGI_SCP_IMR) +#define CORGI_SCP_REG_ISR CORGI_SCP_REG(CORGI_SCP_ISR) +#define CORGI_SCP_REG_GPCR CORGI_SCP_REG(CORGI_SCP_GPCR) +#define CORGI_SCP_REG_GPWR CORGI_SCP_REG(CORGI_SCP_GPWR) +#define CORGI_SCP_REG_GPRR CORGI_SCP_REG(CORGI_SCP_GPRR) + +#define CORGI_SCP_GPCR_PA22 ( 1 << 12 ) +#define CORGI_SCP_GPCR_PA21 ( 1 << 11 ) +#define CORGI_SCP_GPCR_PA20 ( 1 << 10 ) +#define CORGI_SCP_GPCR_PA19 ( 1 << 9 ) +#define CORGI_SCP_GPCR_PA18 ( 1 << 8 ) +#define CORGI_SCP_GPCR_PA17 ( 1 << 7 ) +#define CORGI_SCP_GPCR_PA16 ( 1 << 6 ) +#define CORGI_SCP_GPCR_PA15 ( 1 << 5 ) +#define CORGI_SCP_GPCR_PA14 ( 1 << 4 ) +#define CORGI_SCP_GPCR_PA13 ( 1 << 3 ) +#define CORGI_SCP_GPCR_PA12 ( 1 << 2 ) +#define CORGI_SCP_GPCR_PA11 ( 1 << 1 ) + + +/* + * GPIOs + */ +#define CORGI_SCP_LED_GREEN CORGI_SCP_GPCR_PA11 +#define CORGI_SCP_SWA CORGI_SCP_GPCR_PA12 +#define CORGI_SCP_SWB CORGI_SCP_GPCR_PA13 +#define CORGI_SCP_MUTE_L CORGI_SCP_GPCR_PA14 +#define CORGI_SCP_MUTE_R CORGI_SCP_GPCR_PA15 +#define CORGI_SCP_AKIN_PULLUP CORGI_SCP_GPCR_PA16 +#define CORGI_SCP_APM_ON CORGI_SCP_GPCR_PA17 +#define CORGI_SCP_BACKLIGHT_CONT CORGI_SCP_GPCR_PA18 +#define CORGI_SCP_MIC_BIAS CORGI_SCP_GPCR_PA19 + + +#define CORGI_SCP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \ + CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \ + CORGI_SCP_MIC_BIAS ) +#define CORGI_SCP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) +#define CORGI_GPIO_CO 16 + + +/* + * Flash Memory mappings + * + * We have the following mapping: + * phys virt + * boot ROM 00000000 ef000000 + * NAND Flash 0C000000 f2100000 + */ +#define NAND_FLASH_REG_BASE 0xf2100000 +#define CORGI_CPLD_REG(ofst) (*(volatile unsigned char*)(NAND_FLASH_REG_BASE+(ofst))) + +/* register offset */ +#define CORGI_ECCLPLB 0x00 /* line parity 7 - 0 bit */ +#define CORGI_ECCLPUB 0x04 /* line parity 15 - 8 bit */ +#define CORGI_ECCCP 0x08 /* column parity 5 - 0 bit */ +#define CORGI_ECCCNTR 0x0C /* ECC byte counter */ +#define CORGI_ECCCLRR 0x10 /* cleare ECC */ +#define CORGI_FLASHIO 0x14 /* Flash I/O */ +#define CORGI_FLASHCTL 0x18 /* Flash Control */ + +/* Flash control bit */ +#define CORGI_FLRYBY (1 << 5) +#define CORGI_FLCE1 (1 << 4) +#define CORGI_FLWP (1 << 3) +#define CORGI_FLALE (1 << 2) +#define CORGI_FLCLE (1 << 1) +#define CORGI_FLCE0 (1 << 0) + + + + +/* +CORGI_ * LED + */ +#define CORGI_GPIO_LED_ORANGE (13) +//#define CORGI_SCP_LED_GREEN CORGI_SCP_GPCR_PA11 + + +/* + * GPIOs + */ +/* PXA GPIOs */ +#define CORGI_GPIO_KEY_INT (0) /* key interrupt */ +#define CORGI_GPIO_AC_IN (1) +#define CORGI_GPIO_TP_INT (5) /* Touch Panel interrupt */ +#define CORGI_GPIO_WAKEUP (3) +#define CORGI_GPIO_IR_ON (22) +#define CORGI_GPIO_AK_INT (4) // Remote Controller +#define CORGI_GPIO_HP_IN GPIO_AK_INT +#define CORGI_GPIO_CF_IRQ (17) +//#define CORGI_GPIO_CF_PRDY (17) +#define CORGI_GPIO_LED_ORANGE (13) +#define CORGI_GPIO_CF_CD (14) +#define CORGI_GPIO_SD_PWR (33) +#define CORGI_GPIO_nSD_CLK (6) +#define CORGI_GPIO_nSD_WP (7) +#define CORGI_GPIO_nSD_INT (10) +#define CORGI_GPIO_nSD_DETECT (9) +#define CORGI_GPIO_MAIN_BAT_LOW (11) +#define CORGI_GPIO_BAT_COVER (11) +#define CORGI_GPIO_ADC_TEMP_ON (21) +#define CORGI_GPIO_CHRG_ON (38) +#define CORGI_GPIO_CHRG_FULL (16) +#define CORGI_GPIO_USB_PULLUP (45) +#define CORGI_GPIO_HSYNC (44) + +/* KeyBoard */ +#define CORGI_KEY_STROBE_NUM (12) +#define CORGI_KEY_SENSE_NUM (8) +#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc) +#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000) +#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26) +#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003) +#define CORGI_GPIO_LOW_SENSE_LSHIFT (6) +#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a)) +#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a)) +#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0) +#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000) +#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f) +#define CORGI_GPIO_KEY_SENSE(a) (58+(a)) + + +/* + * Interrupts + */ +/* PXA GPIOs */ +#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0) +#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1) +#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4) +#define CORGI_IRQ_GPIO_HP_IN IRQ_GPIO_AK_INT +#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5) +#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3) +#define CORGI_IRQ_GPIO_CO IRQ_GPIO(16) +#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) +#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14) +#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10) +#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) +#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11) +#define CORGI_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(58+(a)) + + +// CS +#define CORGI_CS_MAX1111 1 +#define CORGI_CS_ADS7846 2 +#define CORGI_CS_LZ9JG18 3 + +#define FLASH_MEM_BASE 0xa0000a00 +#define FLASH_DATA(adr) (*(volatile unsigned int*)(FLASH_MEM_BASE+(adr))) +#define FLASH_MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a ) + +// COMADJ +#define FLASH_COMADJ_MAJIC FLASH_MAGIC_CHG('C','M','A','D') +#define FLASH_COMADJ_MAGIC_ADR 0x00 +#define FLASH_COMADJ_DATA_ADR 0x04 + +// PHAD +#define FLASH_PHAD_MAJIC FLASH_MAGIC_CHG('P','H','A','D') +#define FLASH_PHAD_MAGIC_ADR 0x38 +#define FLASH_PHAD_DATA_ADR 0x3C + +typedef struct sharpsl_flash_param_info { + unsigned int comadj_keyword; + unsigned int comadj; + + unsigned int uuid_keyword; + unsigned char uuid[16]; + + unsigned int touch_keyword; + unsigned int touch1; + unsigned int touch2; + unsigned int touch3; + unsigned int touch4; + + unsigned int adadj_keyword; + unsigned int adadj; + + unsigned int phad_keyword; + unsigned int phadadj; +} sharpsl_flash_param_info; + + +int sharpsl_get_comadj(void); +int sharpsl_get_phadadj(void); + +// CS +#define CS_MAX1111 1 +#define CS_ADS7846 2 +#define CS_LZ9JG18 3 + + +#endif /* __ASM_ARCH_CORGI_H */ + diff -uNr linux-2.6.7-1/include/asm-arm/arch-pxa/pxa-regs.h linux-2.6.7/include/asm-arm/arch-pxa/pxa-regs.h --- linux-2.6.7-1/include/asm-arm/arch-pxa/pxa-regs.h 2004-06-21 12:27:07.000000000 +0100 +++ linux-2.6.7/include/asm-arm/arch-pxa/pxa-regs.h 2004-06-21 12:32:49.000000000 +0100 @@ -1472,6 +1472,30 @@ /* * SSP Serial Port Registers */ + +#define SSCR0_DSS 0 +#define SSCR0_FRF 4 +#define SSCR0_ECS 6 +#define SSCR0_SSE 7 +#define SSCR0_SCR 8 + +#define SSCR1_RIE 0 +#define SSCR1_TIE 1 +#define SSCR1_LBM 2 +#define SSCR1_SPO 3 +#define SSCR1_SPH 4 +#define SSCR1_MWDS 5 +#define SSCR1_TFT 6 +#define SSCR1_RFT 10 + +#define SSSR_TNF_MSK (1u << 2) +#define SSSR_RNE_MSK (1u << 3) +#define SSSR_BSY_MSK (1u << 4) +#define SSSR_TFS_MSK (1u << 5) +#define SSSR_RFS_MSK (1u << 6) +#define SSSR_ROR_MSK (1u << 7) +#define SSSR_TFL_MSK (0xfu << 8) +#define SSSR_RFL_MSK (0xfu << 12) #define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */ #define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */ @@ -1479,27 +1503,27 @@ #define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ #define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ -#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ -#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ -#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ -#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ -#define SSCR0_National (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ -#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ -#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ -#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ -#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ +//#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ +//#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ +//#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ +//#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ +//#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ +//#define SSCR0_National (0x2 << 4) /* National Microwire */ +//#define SSCR0_ECS (1 << 6) /* External clock select */ +//#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ +//#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ +//#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ + +//#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ +//#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ +//#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ +//#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ +//#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ +//#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ +//#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ +//#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ +//#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ +//#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ @@ -1508,7 +1532,6 @@ #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ - /* * MultiMediaCard (MMC) controller */