 arch/arm/mach-pxa/lpc.c             |  152 +++++++++++++++++++++++++++++++++++
 drivers/input/serio/Kconfig         |    2 
 drivers/input/serio/i8042-ite8711.h |   89 ++++++++++++++++++++
 drivers/input/serio/i8042.h         |    2 
 include/asm-arm/hardware/it8711.h   |   33 ++++++++
 5 files changed, 277 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/lpc.c b/arch/arm/mach-pxa/lpc.c
new file mode 100644
index 0000000..3a9d960
--- /dev/null
+++ b/arch/arm/mach-pxa/lpc.c
@@ -0,0 +1,152 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	ITE Semi IT8712 Super I/O functions.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or support@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/hardware/it8711.h>
+#include <asm/hardware/it8152.h>
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+
+void LPCEnterMBPnP(void)
+{
+	int i;
+	unsigned char key[4] = {0x87, 0x87};
+
+	for (i = 0; i<2; i++)
+		outb(key[i], LPC_KEY_ADDR);
+
+}
+
+
+
+void LPCExitMBPnP(void)
+{
+	outb(0x02, LPC_KEY_ADDR);
+	outb(0x02, LPC_DATA_ADDR);
+}
+
+void LPCSetConfig(char LdnNumber, char Index, char data)
+{
+	LPCEnterMBPnP();				// Enter IT8711 MB PnP mode
+	outb(0x07, LPC_KEY_ADDR);
+	outb(LdnNumber, LPC_DATA_ADDR);
+	outb(Index, LPC_KEY_ADDR);	
+	outb(data, LPC_DATA_ADDR);
+	LPCExitMBPnP();
+}	 
+
+char LPCGetConfig(char LdnNumber, char Index)
+{
+	char rtn;
+
+	LPCEnterMBPnP();				// Enter IT8711 MB PnP mode
+	outb(0x07, LPC_KEY_ADDR);
+	outb(LdnNumber, LPC_DATA_ADDR);
+	outb(Index, LPC_KEY_ADDR);	
+	rtn = inb(LPC_DATA_ADDR);
+	LPCExitMBPnP();
+	return rtn;
+}
+
+int SearchIT8711(void)
+{
+	unsigned char Id1, Id2;
+	unsigned short Id;
+
+	LPCEnterMBPnP();
+	outb(0x20, LPC_KEY_ADDR); //chip id byte 1 
+	Id1 = inb(LPC_DATA_ADDR);
+	outb(0x21, LPC_KEY_ADDR); // chip id byte 2 
+	Id2 = inb(LPC_DATA_ADDR);
+	Id = (Id1 << 8) | Id2;
+	LPCExitMBPnP();
+//	printk("Reading 8711 ID result: %x\n", Id); 
+	if (Id == 0x8711) 
+		return TRUE;
+	else
+		return FALSE;
+}
+
+
+void InitLPCInterface(void)
+{
+	unsigned char bus, dev_fn;
+	unsigned long data;
+	int i;
+
+	/* LPC function and not GPIO */
+	IT8152_GPIO_GPCR12 = 0;
+	IT8152_GPIO_GPCR34 = 0;
+
+	bus = 0;
+	dev_fn = 0xa; 
+
+
+	/* pci cmd, SERR# Enable */
+ 	IT8152_PCI_CFG_ADDR =   
+		 ((bus         << IT_BUSNUM_SHF)   |
+		 (dev_fn      << IT_FUNCNUM_SHF) |
+		 ((0x4 / 4) << IT_REGNUM_SHF));
+	data  = IT8152_PCI_CFG_DATA;
+	data |= 0x0100;
+	IT8152_PCI_CFG_ADDR =   
+		 ((bus         << IT_BUSNUM_SHF)   |
+		 (dev_fn      << IT_FUNCNUM_SHF) |
+		 ((0x4 / 4) << IT_REGNUM_SHF));
+	IT8152_PCI_CFG_DATA = data;
+
+	/* setup serial irq control register */
+ 	IT8152_PCI_CFG_ADDR =   
+		 ((bus         << IT_BUSNUM_SHF)   |
+		 (dev_fn      << IT_FUNCNUM_SHF) |
+		 ((0x48 / 4) << IT_REGNUM_SHF));
+	data  = IT8152_PCI_CFG_DATA;
+	data  = (data & 0xffff00ff) | 0xc400;
+	IT8152_PCI_CFG_ADDR =   
+		 ((bus         << IT_BUSNUM_SHF)   |
+		 (dev_fn      << IT_FUNCNUM_SHF) |
+		 ((0x48 / 4) << IT_REGNUM_SHF));
+	IT8152_PCI_CFG_DATA = data;
+
+	/* Enable subtructive decoding */
+ 	IT8152_PCI_CFG_ADDR =   
+		 ((bus         << IT_BUSNUM_SHF)   |
+		 (dev_fn      << IT_FUNCNUM_SHF) |
+		 ((0x4C / 4) << IT_REGNUM_SHF));
+	IT8152_PCI_CFG_DATA = 0x3f0000f3;
+}
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index 98acf17..49d562e 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -21,7 +21,7 @@ if SERIO
 config SERIO_I8042
 	tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
 	default y
-	depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K
+	depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST || CM_X255) && !M68K
 	---help---
 	  i8042 is the chip over which the standard AT keyboard and PS/2
 	  mouse are connected to the computer. If you use these devices,
diff --git a/drivers/input/serio/i8042-ite8711.h b/drivers/input/serio/i8042-ite8711.h
new file mode 100644
index 0000000..9e919e1
--- /dev/null
+++ b/drivers/input/serio/i8042-ite8711.h
@@ -0,0 +1,89 @@
+#ifndef _I8042_CM_X_2XX_IO_H
+#define _I8042_CM_X_2XX_IO_H
+
+#include <linux/config.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/cm-x255.h>
+
+#include <asm/hardware/it8152.h>
+#include <asm/hardware/it8711.h>
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+/*
+ * Names.
+ */
+
+#define I8042_KBD_PHYS_DESC "it8711/serio0"
+#define I8042_AUX_PHYS_DESC "it8711/serio1"
+#define I8042_MUX_PHYS_DESC "it8711/serio%d"
+
+/*
+ * IRQs.
+ */
+# define I8042_KBD_IRQ	KEYBOARD_IRQ
+# define I8042_AUX_IRQ	MOUSE_IRQ
+
+
+/*
+ * Register numbers.
+ */
+
+#define I8042_COMMAND_REG	KBD_COMMAND
+#define I8042_STATUS_REG	KBD_COMMAND
+#define I8042_DATA_REG		KBD_DATA
+
+static inline int i8042_read_data(void)
+{
+	return inb(I8042_DATA_REG);
+}
+
+static inline int i8042_read_status(void)
+{
+	return inb(I8042_STATUS_REG);
+}
+
+static inline void i8042_write_data(int val)
+{
+	outb(val, I8042_DATA_REG);
+}
+
+static inline void i8042_write_command(int val)
+{
+	outb(val, I8042_COMMAND_REG);
+}
+
+static inline int i8042_platform_init(void)
+{
+/*
+ * On some platforms touching the i8042 data register region can do really
+ * bad things. Because of this the region is always reserved on such boxes.
+ */
+#if !defined(__sh__) && !defined(__alpha__) && !defined(__mips__) && !defined(CONFIG_PPC64)
+	if (!request_region(I8042_DATA_REG, 16, "i8042"))
+		return -EBUSY;
+#endif
+
+        i8042_reset = 1;
+
+#if defined(CONFIG_PPC64)
+	if (check_legacy_ioport(I8042_DATA_REG))
+		return -EBUSY;
+	if (!request_region(I8042_DATA_REG, 16, "i8042"))
+		return -EBUSY;
+#endif
+	return 0;
+}
+
+static inline void i8042_platform_exit(void)
+{
+#if !defined(__sh__) && !defined(__alpha__) && !defined(CONFIG_PPC64)
+	release_region(I8042_DATA_REG, 16);
+#endif
+}
+
+#endif /* _I8042_CM_X_2XX_IO_H */
diff --git a/drivers/input/serio/i8042.h b/drivers/input/serio/i8042.h
index af526ab..3ae1333 100644
--- a/drivers/input/serio/i8042.h
+++ b/drivers/input/serio/i8042.h
@@ -24,6 +24,8 @@ #elif defined(CONFIG_SPARC)
 #include "i8042-sparcio.h"
 #elif defined(CONFIG_X86) || defined(CONFIG_IA64)
 #include "i8042-x86ia64io.h"
+#elif defined(CONFIG_CM_X255)
+#include "i8042-ite8711.h"
 #else
 #include "i8042-io.h"
 #endif
diff --git a/include/asm-arm/hardware/it8711.h b/include/asm-arm/hardware/it8711.h
new file mode 100644
index 0000000..7238697
--- /dev/null
+++ b/include/asm-arm/hardware/it8711.h
@@ -0,0 +1,33 @@
+#ifndef __IT8711_H__
+#define __IT8711_H__
+
+#define LPC_BASE_ADDR	IT8152_IO_BASE
+
+/* MB PnP configuration register  */
+#define LPC_KEY_ADDR	(LPC_BASE_ADDR + 0x2E)
+#define LPC_DATA_ADDR	(LPC_BASE_ADDR + 0x2F)
+
+/* Device LDN */
+#define LDN_NONE	0x00
+#define LDN_SERIAL1	0x01
+#define LDN_SERIAL2	0x02
+#define LDN_PARALLEL	0x03
+#define LDN_KEYBOARD	0x05
+#define LDN_MOUSE	0x06
+#define LDN_FLOPPY	0x07
+
+#define IT8711_UART1_PORT      (LPC_BASE_ADDR + 0x3F8)
+#define IT8711_UART2_PORT      (LPC_BASE_ADDR + 0x2F8)
+
+#define KBD_COMMAND	(LPC_BASE_ADDR + 0x64)
+#define KBD_DATA	(LPC_BASE_ADDR + 0x60)
+
+
+#ifndef ASM_ONLY
+
+void LPCSetConfig(char LdnNumber, char Index, char data);
+char LPCGetConfig(char LdnNumber, char Index);
+
+#endif
+
+#endif

