diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d8f9eaa..b033fb8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -632,7 +632,7 @@ config XIP_PHYS_ADDR endmenu -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1 || ARCH_PXA) menu "CPU Frequency scaling" @@ -659,6 +659,18 @@ config CPU_FREQ_INTEGRATOR If in doubt, say Y. +config CPU_FREQ_PXA25x + bool + select CPU_FREQ_TABLE + depends on CPU_FREQ && PXA25x + default y + +config CPU_FREQ_PXA27x + bool + select CPU_FREQ_TABLE + depends on CPU_FREQ && PXA27x + default y + endmenu endif diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index b5c1743..85df8c1 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -25,6 +25,10 @@ led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o obj-$(CONFIG_LEDS) += $(led-y) +# CPU freq support +obj-$(CONFIG_CPU_FREQ_PXA25x) += cpu-pxa25x.o +obj-$(CONFIG_CPU_FREQ_PXA27x) += cpu-pxa27x.o + # Misc features obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_PXA_KEYS) += pxa_keys.o diff --git a/arch/arm/mach-pxa/cpu-pxa25x.c b/arch/arm/mach-pxa/cpu-pxa25x.c new file mode 100644 index 0000000..499a342 --- /dev/null +++ b/arch/arm/mach-pxa/cpu-pxa25x.c @@ -0,0 +1,353 @@ +/* + * linux/arch/arm/mach-pxa/cpu-pxa.c + * + * Copyright (C) 2002,2003 Intrinsyc Software + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * History: + * 31-Jul-2002 : Initial version [FB] + * 29-Jan-2003 : added PXA255 support [FB] + * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) + * 18-Jul-2005 : updated for latest kernel (2.6.13-rc), cleanup for submission + * (Ian Campbell, Arcom Control Systems) + * + * Note: + * This driver may change the memory bus clock rate, but will not do any + * platform specific access timing changes... for example if you have flash + * memory connected to CS0, you will need to register a platform specific + * notifier which will adjust the memory access strobes to maintain a + * minimum strobe width. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "pxa25x", msg) + +struct pxa_freqs { + unsigned int khz; + unsigned int membus; + unsigned int cccr; + unsigned int div2; +}; + +/* Define the refresh period in mSec for the SDRAM and the number of rows */ +#define SDRAM_TREF 64 /* standard 64ms SDRAM */ +#define SDRAM_ROWS 8192 /* 64MB=8192 32MB=4096 */ +#define MDREFR_DRI(x) ((x*SDRAM_TREF)/(SDRAM_ROWS*32)) + +#define CCLKCFG_TURBO 0x1 +#define CCLKCFG_FCS 0x2 +#define PXA25x_MIN_FREQ 99532 +#define PXA25x_MAX_FREQ 398131 +#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) +#define MDREFR_DRI_MASK 0xFFF + +/* Use the run mode frequencies for performance */ +static struct pxa_freqs pxa25x_performance_freqs[] = { + /* CPU MEMBUS CCCR DIV2 */ + {99532, 99532, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ + {132710, 132710, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ + {199065, 99532, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ + {265421, 132710, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */ + {331776, 165888, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ + {398131, 99532, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */ +}; + +static struct cpufreq_frequency_table pxa25x_performance_freq_table[ARRAY_SIZE(pxa25x_performance_freqs)+1]; + +/* Use the turbo mode frequencies for powersave */ +static struct pxa_freqs pxa25x_powersave_freqs[] = { + /* CPU MEMBUS CCCR DIV2 */ + {99532, 99532, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */ + {199065, 99532, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */ + {298598, 99532, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */ + {398131, 99532, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */ +}; + +static struct cpufreq_frequency_table pxa25x_powersave_freq_table[ARRAY_SIZE(pxa25x_powersave_freqs)+1]; + +extern unsigned get_clk_frequency_khz(int info); + +static unsigned int max_frequency = PXA25x_MAX_FREQ; +static int performance = 0; + +/* + * This option can be used if you have one of the 200MHz PXA25x parts by adding + * cpu_pxa25x.max_frequency=199065 to the kernel command line + */ +module_param(max_frequency, int, 0); +MODULE_PARM_DESC(max_frequency, "Set the maximum cpu frequency"); + +module_param(performance, int, 0); +MODULE_PARM_DESC(performance, "Use performance instead of powersave frequency tables"); + +static void pxa_select_freq_table(struct cpufreq_policy *policy, + struct pxa_freqs ** settings, + struct cpufreq_frequency_table **table) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + + if (performance) { + dprintk("selecting performance tables\n"); + cpufreq_frequency_table_get_attr(pxa25x_performance_freq_table, policy->cpu); + if (settings) + *settings = pxa25x_performance_freqs; + if (table) + *table = pxa25x_performance_freq_table; + } else { + dprintk("selecting powersave tables\n"); + cpufreq_frequency_table_get_attr(pxa25x_powersave_freq_table, policy->cpu); + if (settings) + *settings = pxa25x_powersave_freqs; + if (table) + *table = pxa25x_powersave_freq_table; + } +} + +/* find a valid frequency point */ +static int pxa_verify_policy(struct cpufreq_policy *policy) +{ + int ret; + struct cpufreq_frequency_table *pxa_freqs_table; + + pxa_select_freq_table(policy, NULL, &pxa_freqs_table); + + ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); + + dprintk("verified CPU policy: %dKhz min to %dKhz max\n", + policy->min, policy->max); + + return ret; +} + +static int pxa_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + int idx; + struct cpufreq_freqs freqs; + struct pxa_freqs *pxa_freq_settings; + struct cpufreq_frequency_table *pxa_freqs_table; + unsigned long flags; + unsigned int unused; + unsigned int preset_mdrefr, postset_mdrefr; + void *ramstart; + + /* Get the current policy */ + pxa_select_freq_table(policy, &pxa_freq_settings, &pxa_freqs_table); + + /* Lookup the next frequency */ + if (cpufreq_frequency_table_target(policy, pxa_freqs_table, + target_freq, relation, &idx)) + return -EINVAL; + + freqs.old = get_clk_frequency_khz(0); + freqs.new = pxa_freq_settings[idx].khz; + freqs.cpu = policy->cpu; + + if (freqs.new == freqs.old && pxa_freq_settings[idx].cccr == CCCR) + return 0; + + dprintk("changing CPU frequency to %d.%03d Mhz (SDRAM %d Mhz, CCCR %#04x)\n", + freqs.new / 1000, freqs.new % 1000, + (pxa_freq_settings[idx].div2) ? + (pxa_freq_settings[idx].membus / 2000) : + (pxa_freq_settings[idx].membus / 1000), + pxa_freq_settings[idx].cccr); + + ramstart = phys_to_virt(0xa0000000); + + /* + * Tell everyone what we're about to do... + * you should add a notify client with any platform specific + * Vcc changing capability + */ + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + /* Calculate the next MDREFR. If we're slowing down the SDRAM clock + * we need to preset the smaller DRI before the change. If we're speeding + * up we need to set the larger DRI value after the change. + */ + preset_mdrefr = postset_mdrefr = MDREFR; + if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) { + preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | + MDREFR_DRI(pxa_freq_settings[idx].membus); + } + postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | + MDREFR_DRI(pxa_freq_settings[idx].membus); + + /* If we're dividing the memory clock by two for the SDRAM clock, this + * must be set prior to the change. Clearing the divide must be done + * after the change. + */ + if (pxa_freq_settings[idx].div2) { + preset_mdrefr |= MDREFR_DB2_MASK; + postset_mdrefr |= MDREFR_DB2_MASK; + } else { + postset_mdrefr &= ~MDREFR_DB2_MASK; + } + + local_irq_save(flags); + + /* Set new the CCCR */ + CCCR = pxa_freq_settings[idx].cccr; + + __asm__ __volatile__(" \ + ldr r4, [%1] ; /* load MDREFR */ \ + b 2f ; \ + .align 5 ; \ +1: \ + str %4, [%1] ; /* preset the MDREFR */ \ + mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */ \ + str %5, [%1] ; /* postset the MDREFR */ \ + \ + b 3f ; \ +2: b 1b ; \ +3: nop ; \ + " + : "=&r"(unused) + : "r"(&MDREFR), "r"(CCLKCFG_TURBO | CCLKCFG_FCS), + "r"(ramstart), "r"(preset_mdrefr), + "r"(postset_mdrefr) + : "r4", "r5"); + local_irq_restore(flags); + + /* + * Tell everyone what we've just done... + * you should add a notify client with any platform specific + * SDRAM refresh timer adjustments + */ + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +static unsigned int pxa_cpufreq_get(unsigned int cpu) +{ + return get_clk_frequency_khz(0); +} + +static int pxa_cpufreq_init(struct cpufreq_policy *policy) +{ + int i; + + if (policy->cpu != 0) + return -ENODEV; + + /* set default policy and cpuinfo */ + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cpuinfo.max_freq = max_frequency; + policy->cpuinfo.min_freq = PXA25x_MIN_FREQ; + policy->cpuinfo.transition_latency = 1000000; /* FIXME: 1 ms, assumed */ + policy->cur = get_clk_frequency_khz(0); /* current freq */ + policy->min = policy->max = policy->cur; + policy->min = pxa25x_powersave_freqs[0].khz; + policy->max = pxa25x_powersave_freqs[sizeof(pxa25x_powersave_freqs)/sizeof(*pxa25x_powersave_freqs)-1].khz; + + /* Generate the run cpufreq_frequency_table struct */ + for (i = 0; i < ARRAY_SIZE(pxa25x_performance_freqs); i++) { + pxa25x_performance_freq_table[i].frequency = pxa25x_performance_freqs[i].khz; + pxa25x_performance_freq_table[i].index = i; + } + pxa25x_performance_freq_table[i].frequency = CPUFREQ_TABLE_END; + + /* Generate the turbo cpufreq_frequency_table struct */ + for (i = 0; i < ARRAY_SIZE(pxa25x_powersave_freqs); i++) { + pxa25x_powersave_freq_table[i].frequency = pxa25x_powersave_freqs[i].khz; + pxa25x_powersave_freq_table[i].index = i; + } + pxa25x_powersave_freq_table[i].frequency = CPUFREQ_TABLE_END; + + /* calls cpufreq_frequency_table_get_attr */ + pxa_select_freq_table(policy, NULL, NULL); + + printk(KERN_INFO "pxa25x: CPU frequency change support initialized (%s tables)\n", + performance ? "performance" : "powersave"); + + return 0; +} + +static ssize_t show_pxa25x_freq_model_attr(struct cpufreq_policy * policy, char *buf) +{ + return sprintf (buf, "%s\n", performance ? "performance" : "powersave"); +} + +static ssize_t store_pxa25x_freq_model_attr(struct cpufreq_policy * policy, const char *buf, size_t count) +{ + unsigned int ret; + char str[16]; + + ret = sscanf(buf, "%15s", str); + if (ret != 1) + return -EINVAL; + + if (strnicmp(str,"performance",16)==0) + performance = 1; + else if (strnicmp(str,"powersave",16)==0) + performance = 0; + else + return -EINVAL; + + ret = cpufreq_update_policy(policy->cpu); + + return ret ? ret : count; +} + +struct freq_attr pxa25x_freq_model_attr = { + .attr = { .name = "pxa25x_freq_model", .mode = 0644, .owner=THIS_MODULE }, + .show = show_pxa25x_freq_model_attr, + .store = store_pxa25x_freq_model_attr, +}; + +static struct freq_attr* pxa_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + &pxa25x_freq_model_attr, + NULL, +}; + +static struct cpufreq_driver pxa_cpufreq_driver = { + .verify = pxa_verify_policy, + .target = pxa_set_target, + .init = pxa_cpufreq_init, + .get = pxa_cpufreq_get, + .name = "pxa25x", + .attr = pxa_cpufreq_attr, +}; + +static int __init pxa_cpu_init(void) +{ + return cpufreq_register_driver(&pxa_cpufreq_driver); +} + +static void __exit pxa_cpu_exit(void) +{ + cpufreq_unregister_driver(&pxa_cpufreq_driver); +} + +MODULE_AUTHOR("Intrinsyc Software Inc."); +MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture"); +MODULE_LICENSE("GPL"); +module_init(pxa_cpu_init); +module_exit(pxa_cpu_exit); diff --git a/arch/arm/mach-pxa/cpu-pxa27x.c b/arch/arm/mach-pxa/cpu-pxa27x.c new file mode 100644 index 0000000..5ffe0ef --- /dev/null +++ b/arch/arm/mach-pxa/cpu-pxa27x.c @@ -0,0 +1,329 @@ +/* + * linux/arch/arm/mach-pxa/cpu-pxa27x.c + * + * Copyright (C) 2002,2003 Intrinsyc Software + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * History: + * 31-Jul-2002 : Initial version [FB] + * 29-Jan-2003 : added PXA255 support [FB] + * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) + * 18-Jul-2005 : updated for latest kernel (2.6.13-rc), cleanup for submission + * (Ian Campbell, Arcom Control Systems) + * 11-Jan-2006 : v2.6, support for PXA27x processor up to 624MHz (Bill Reese, Hewlett Packard) + * 1-May-2006 : v2.6.16, resynced with current kernel and split from pxa25x driver + * (Steven Newbury) + * + * Note: + * This driver may change the memory bus clock rate, but will not do any + * platform specific access timing changes... for example if you have flash + * memory connected to CS0, you will need to register a platform specific + * notifier which will adjust the memory access strobes to maintain a + * minimum strobe width. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * This comes from generic.h in this directory. + */ +extern unsigned int get_clk_frequency_khz(int info); + +#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "pxa27x", msg) + +struct pxa27x_freqs { + unsigned int khz; /* CPU frequency */ + unsigned int membus; /* memory bus frequency */ + unsigned int cccr; /* new CCCR setting */ + unsigned int div2; /* alter memory controller settings to divide by 2 */ + unsigned int cclkcfg; /* new CCLKCFG setting */ +}; + +/* Define the refresh period in mSec for the SDRAM and the number of rows */ +#define SDRAM_TREF 64 /* standard 64ms SDRAM */ +#define SDRAM_ROWS 8192 /* 64MB=8192 32MB=4096 */ +#define MDREFR_DRI(x) ((x*SDRAM_TREF)/(SDRAM_ROWS*32)) + +#define CCLKCFG_TURBO 0x1 +#define CCLKCFG_FCS 0x2 +#define CCLKCFG_HALFTURBO 0x4 +#define CCLKCFG_FASTBUS 0x8 +#define PXA27x_MIN_FREQ 104000 +#define PXA27x_MAX_FREQ 416000 +#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) +#define MDREFR_DRI_MASK 0xFFF +#define PXA25x_CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS + +/* + * For the PXA27x: + * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. + * + * A = 0 => memory controller clock from table 3-7, + * A = 1 => memory controller clock = system bus clock + * Run mode frequency = 13 MHz * L + * Turbo mode frequency = 13 MHz * L * N + * System bus frequency = 13 MHz * L / (B + 1) + * System initialized by bootldr to: + * + * In CCCR: + * A = 1 + * L = 16 oscillator to run mode ratio + * 2N = 6 2 * (turbo mode to run mode ratio) + * + * In CCLKCFG: + * B = 1 Fast bus mode + * HT = 0 Half-Turbo mode + * T = 1 Turbo mode + * + * For now, just support some of the combinations in table 3-7 of + * PXA27x Processor Family Developer's Manual to simplify frequency + * change sequences. + * + * Specify 2N in the PXA27x_CCCR macro, not N! + */ +#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) +#define PXA27x_CCLKCFG(B, HT, T) (B << 3 | HT << 2 | CCLKCFG_FCS | T) + +static struct pxa27x_freqs pxa27x_freqs[] = { + /* CPU MEMBUS CCCR DIV2 */ + {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CCLKCFG(1, 0, 1)}, + {156000, 104000, PXA27x_CCCR(1, 8, 6), 0, PXA27x_CCLKCFG(1, 1, 1)}, + {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CCLKCFG(0, 0, 1)}, + {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CCLKCFG(1, 0, 1)}, + {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CCLKCFG(1, 0, 1)}, + {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CCLKCFG(1, 0, 1)}, + {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CCLKCFG(1, 0, 1)} +}; + +static struct cpufreq_frequency_table pxa27x_freq_table[ARRAY_SIZE(pxa27x_freqs)+1]; + +extern unsigned get_clk_frequency_khz(int info); + +static unsigned int max_frequency = PXA27x_MAX_FREQ; + +/* + * This option can be used if your machine can not operate faster than 416MHz + * for example cpu_pxa27x.max_frequency=416000 to the kernel command line, + * My SL-C3100 runs fine at 520Mhz, overclock at your own risk. FIXME: Some + * defaults for various machines really should be added. Use the userspace + * governer and set /sys/device/system/cpu/cpu0/cpufreq/scaling_max_freq to + * a suitable maximum for your machine. + */ + +module_param(max_frequency, int, 0); +MODULE_PARM_DESC(max_frequency, "Set the maximum cpu frequency"); + +/* find a valid frequency point */ +static int pxa27x_verify_policy(struct cpufreq_policy *policy) +{ + int ret; + + ret = cpufreq_frequency_table_verify(policy, pxa27x_freq_table); + + dprintk("verified CPU policy: %dKhz min to %dKhz max\n", + policy->min, policy->max); + + return ret; +} + +static int pxa27x_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + int idx; + struct cpufreq_freqs freqs; + unsigned long flags; + unsigned int unused; + void *ramstart; + unsigned int preset_mdrefr, postset_mdrefr, cclkcfg; + + /* Lookup the next frequency */ + if (cpufreq_frequency_table_target(policy, pxa27x_freq_table, + target_freq, relation, &idx)) + return -EINVAL; + + freqs.old = get_clk_frequency_khz(0); + freqs.new = pxa27x_freqs[idx].khz; + freqs.cpu = policy->cpu; + + if (freqs.new == freqs.old && pxa27x_freqs[idx].cccr == CCCR) + return 0; + + dprintk("changing CPU frequency to %d.%03d Mhz (SDRAM %d Mhz, CCCR %#04x)\n", + freqs.new / 1000, freqs.new % 1000, + (pxa27x_freqs[idx].div2) ? + (pxa27x_freqs[idx].membus / 2000) : + (pxa27x_freqs[idx].membus / 1000), + pxa27x_freqs[idx].cccr); + + ramstart = phys_to_virt(0xa0000000); + + /* + * Tell everyone what we're about to do... + * you should add a notify client with any platform specific + * Vcc changing capability + */ + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + /* Calculate the next MDREFR. If we're slowing down the SDRAM clock + * we need to preset the smaller DRI before the change. If we're speeding + * up we need to set the larger DRI value after the change. + */ + preset_mdrefr = postset_mdrefr = MDREFR; + if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa27x_freqs[idx].membus)) { + preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | + MDREFR_DRI(pxa27x_freqs[idx].membus); + } + postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | + MDREFR_DRI(pxa27x_freqs[idx].membus); + + /* If we're dividing the memory clock by two for the SDRAM clock, this + * must be set prior to the change. Clearing the divide must be done + * after the change. + */ + if(pxa27x_freqs[idx].div2) { + /* + * Potentially speeding up memory clock, so slow down the memory + * before speeding up the clock. + */ + preset_mdrefr |= MDREFR_DB2_MASK | MDREFR_K0DB4; + preset_mdrefr &= ~MDREFR_K0DB2; + + postset_mdrefr |= MDREFR_DB2_MASK | MDREFR_K0DB4; + postset_mdrefr &= ~MDREFR_K0DB2; + } else { + /* + * Potentially slowing down memory clock. Wait until after the change + * to speed up the memory. + */ + postset_mdrefr &= ~MDREFR_DB2_MASK; + postset_mdrefr &= ~MDREFR_K0DB4; + postset_mdrefr |= MDREFR_K0DB2; + } + + cclkcfg = pxa27x_freqs[idx].cclkcfg; + + local_irq_save(flags); + + /* Set new the CCCR */ + CCCR = pxa27x_freqs[idx].cccr; + + /* + * Should really set both of PMCR[xIDAE] while changing the core frequency + */ + + /* + * TODO: On the PXA27x: If we're setting half-turbo mode and changing the + * core frequency at the same time we must split it up into two operations. + * The current values in the pxa27x_freqs table don't do this, so the code + * is unimplemented. +*/ + + __asm__ __volatile__(" \ + ldr r4, [%1] ; /* load MDREFR */ \ + b 2f ; \ + .align 5 ; \ + 1: \ + str %3, [%1] ; /* preset the MDREFR */ \ + mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */ \ + str %4, [%1] ; /* postset the MDREFR */ \ + \ + b 3f ; \ + 2: b 1b ; \ + 3: nop ; \ + " + : "=&r" (unused) + : "r" (&MDREFR), "r" (cclkcfg), \ + "r" (preset_mdrefr), "r" (postset_mdrefr) + : "r4", "r5"); + local_irq_restore(flags); + + /* + * Tell everyone what we've just done... + * you should add a notify client with any platform specific + * SDRAM refresh timer adjustments + */ + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +static unsigned int pxa27x_cpufreq_get(unsigned int cpu) +{ + return get_clk_frequency_khz(0); +} + +static int pxa27x_cpufreq_init(struct cpufreq_policy *policy) +{ + int i; + + if (policy->cpu != 0) + return -ENODEV; + + /* set default policy and cpuinfo */ + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cpuinfo.max_freq = max_frequency; + policy->cpuinfo.min_freq = PXA27x_MIN_FREQ; + policy->cpuinfo.transition_latency = 10000; /* FIXME: 1 ms, assumed */ + policy->cur = get_clk_frequency_khz(0); /* current freq */ + policy->min = policy->max = policy->cur; + policy->min = pxa27x_freqs[0].khz; + policy->max = pxa27x_freqs[sizeof(pxa27x_freqs)/sizeof(*pxa27x_freqs)-1].khz; + + /* Generate the run cpufreq_frequency_table struct */ + for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++) { + pxa27x_freq_table[i].frequency = pxa27x_freqs[i].khz; + pxa27x_freq_table[i].index = i; + } + pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END; + + printk(KERN_INFO "pxa27x: CPU frequency change support initialized\n"); + + return 0; +} + + +static struct cpufreq_driver pxa27x_cpufreq_driver = { + .verify = pxa27x_verify_policy, + .target = pxa27x_set_target, + .init = pxa27x_cpufreq_init, + .get = pxa27x_cpufreq_get, + .name = "pxa27x", +}; + +static int __init pxa27x_cpu_init(void) +{ + return cpufreq_register_driver(&pxa27x_cpufreq_driver); +} + +static void __exit pxa27x_cpu_exit(void) +{ + cpufreq_unregister_driver(&pxa27x_cpufreq_driver); +} + +MODULE_AUTHOR("Based on pxa25x cpufreq handler by Intrinsyc Software Inc."); +MODULE_DESCRIPTION("CPU frequency changing driver for the PXA27x architecture"); +MODULE_LICENSE("GPL"); +module_init(pxa27x_cpu_init); +module_exit(pxa27x_cpu_exit); diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 1409c5b..415c6f8 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1781,7 +1781,7 @@ #define CKEN __REG(0x41300004) /* Cloc #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ #define CCSR __REG(0x4130000C) /* Core Clock Status Register */ -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define CCCR_N_MASK 0x0780 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */